low power

October 3, 2012

System virtual prototyping

The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.
June 4, 2012

Sleep modes

For a growing number of applications, leakage is a major component of the lifetime energy consumption of an MCU, making it essential to shut the processor core down when it is not needed. Sleep modes help control that.
March 21, 2012

How TI halved the power consumption of Wolverine

Texas Instruments’ MSP430 microcontroller platform has been one of the industry’s leading ultra-low-power architectures for more than a decade. Each generation has been focused on setting new records. The latest, Wolverine, cuts power and energy consumption by more than half.
Article  |  Topics: Embedded - Platforms  |  Tags: , ,   |  Organizations:
March 7, 2012

Envelope tracking for RF power amplifiers in mobile handsets

‘Envelope tracking’ is not a new technique; it has been known about for more than 50 years. But it could greatly help the power consumption challenges once more facing mobile handset design.
Article  |  Topics: PCB - Design Integrity  |  Tags: , , , , ,   |  Organizations:
January 16, 2012

Unified Power Format (UPF)

The IEEE Unified Power Format (UPF) standard is intended to support low-power designs that use switchable power states and power islands.
June 1, 2010

Energy debugging – the next step in MCU software optimization

Knowing where your application is consuming resources is a crucial step in minimizing energy usage. The article describes a toolset developed by high-profile ARM-based microcontroller (MCU) start-up Energy Micro that helps to achieve this overarching goal within the context of a parallel move to 32bit MCU resolution.
Article  |  Topics: EDA - DFT  |  Tags: , ,
June 1, 2010

Winning the power and temperature battle with ESL exploration

The analysis of important power and temperature metrics for chip design is becoming increasingly inefficient when attempted at the register-transfer level. The article proposes the fundamentals of a system-level modeling strategy that will shrink design times, provide more opportunities for architectural exploration, and deliver significant power savings.
Article  |  Topics: EDA - ESL  |  Tags: ,
December 1, 2009

Part 4- Power management in OCP-IP 3.0

According to Moore’s Law, system-on-chips (SoCs) should continually become more complex and integrate more components, enabled by each reduction in silicon technologies. However, power consumption does not follow the linear path implied here due to increasing leakage in deep sub-micron technologies. Hence, new power management techniques are needed to reduce power dissipation as much as […]

Article  |  Topics: EDA - Verification  |  Tags: , ,
September 1, 2009

Extending UPF for incremental growth

Erich Marschner Accellera’s Unified Power Format (UPF) is in production use today, delivering the low-power system-on-chip (SoC) designs that are so much in demand. Building upon that success, IEEE Std 1801-2009 [UPF] offers additional features that address the challenges of low-power design and verification. These include more abstract specifications for power supplies, power states, and […]

Article  |  Topics: EDA - Verification  |  Tags: , ,
May 1, 2009

A holistic approach to low-power verification

The article describes a dedicated low-power functional verification methodology, originally developed at STMicroelectronics (now ST-Ericsson). The article details the content, sequence and effectiveness of the methodology as it was tested on a 45nm system-on-chip design. In order of use, the main components are: A high-level verification language testbench Formal verification Rule checking C function library […]

Article  |  Topics: EDA - Verification  |  Tags: , ,

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