low power

The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.

For a growing number of applications, leakage is a major component of the lifetime energy consumption of an MCU, making it essential to shut the processor core down when it is not needed. Sleep modes help control that.

Texas Instruments’ MSP430 microcontroller platform has been one of the industry’s leading ultra-low-power architectures for more than a decade. Each generation has been focused on setting new records. The latest, Wolverine, cuts power and energy consumption by more than half.

‘Envelope tracking’ is not a new technique; it has been known about for more than 50 years. But it could greatly help the power consumption challenges once more facing mobile handset design.

The IEEE Unified Power Format (UPF) standard is intended to support low-power designs that use switchable power states and power islands.

Knowing where your application is consuming resources is a crucial step in minimizing energy usage. The article describes a toolset developed by high-profile ARM-based microcontroller (MCU) start-up Energy Micro that helps to achieve this overarching goal within the context of a parallel move to 32bit MCU resolution.

The analysis of important power and temperature metrics for chip design is becoming increasingly inefficient when attempted at the register-transfer level. The article proposes the fundamentals of a system-level modeling strategy that will shrink design times, provide more opportunities for architectural exploration, and deliver significant power savings.

According to Moore’s Law, system-on-chips (SoCs) should continually become more complex and integrate more components, enabled by each reduction in silicon technologies. However, power consumption does not follow the linear path implied here due to increasing leakage in deep sub-micron technologies. Hence, new power management techniques are needed to reduce power dissipation as much as […]

Erich Marschner Accellera’s Unified Power Format (UPF) is in production use today, delivering the low-power system-on-chip (SoC) designs that are so much in demand. Building upon that success, IEEE Std 1801-2009 [UPF] offers additional features that address the challenges of low-power design and verification. These include more abstract specifications for power supplies, power states, and […]

The architectures that underpin today’s traditional place-and-route tools are showing their age, largely because their static timing analysis engines cannot handle more than two mode/corner scenarios. Thus limited, the software struggles to effectively implement low-power design techniques beyond such established concepts as clock gating and multiple threshold voltages. Designers run into difficulties when trying to […]