formal verification

Increasingly complex state machines are driving the need for smarter ways of reporting errors such as deadlocks and unreachable code in the source RTL.

Agile development started in the software domain but the methodology shows promise for SoC verification. Formal verification techniques can help implement an Agile flow.

X propagation within RTL simulations can hide fatal bugs. Uncovering and eliminating the effect improves design quality and avoids respins.

Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.

Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.

RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.

When engineers discuss the status and value of the Design Automation Conference (DAC), one topic tends to recur. Fairly or unfairly, the claim is that there has long been an inherent tension between DAC the technical conference and DAC the exhibition. In short, the technical conference has been seen as biased toward tool developers; the […]