EDA

An analysis of what it takes to build true random number generators that can provide a strong cryptographic basis for systems security, especially for IoT devices.

A quick look at Bluetooth Smart and how it can be used to provide network connections in certain classes of IoT application.

New RTL synthesis tools such as Oasys-RTL have greater capacities and shorter runtimes as well as allowing more attention to be spent on achieving QoR

How the powertrain of an electric vehicle is modeled first in software, then elaborated using virtual hardware running target code, to enable virtual FMEA with rich data-gathering and analysis capabilities.

Flash is the ice cream of memory technologies - everybody loves it. But you need to build the right verification environment to extract the greatest benefit.

How fault mode and effect analysis (FMEA) can be performed on a virtual prototype of an automotive system containing mechanical, electrical, analog and digital models, including the microcontroller running the same software as will be used in the car.

The reset state of a design can have a huge impact on the scope and correctness of verification, especially when formal techniques are applied.

Static analysis offers a powerful way of identifying potential X-optimism problems before simulation. The article defines the issue and describes an established solution.

How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs

Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.