EDA

Sequential equivalence checking can help trap errors introduced by clock gate insertion, uninitialised registers, and X propagation issues.

In both data centers and automobiles deep learning is taking hold. But it is a technique that challenges conventional microprocessors, leading system designers to look at alternative architectures for acceleration.

A technique built for software development is now helping hardware engineers master increasingly complex verification flows.

A look at three design challenges for USB Type-C: implementing two SuperSpeed datapaths on a reversible connector; partitioning the design to support multiple USB Type-C variants; and partitioning the management software.

These days, when it comes to innovation: The car's the star - not the stooge.

Accelerating software testing is vital to speeding up embedded system development, especially for Android and Linux systems running on ARM-based hardware. Virtual prototyping strategies, including the use of VDKs, can help.

How to accelerate many aspects of software testing by using virtual prototypes to stand in for target hardware from early in the development cycle.

A look at the challenge of Ethernet verification as data rates rise and the standard is applied in a wider variety of applications.

A look at USB 3.1, which offers data rates of up to 10Gbit/s, and the way that the USB 3.1 protocol has changed to support this rate.

A look at the challenges involved in PCIe verification as the standard evolves to 4.0 and beyond.