DAC 2012: ARM tips subthreshold power-gating technique
Could subthreshold circuitry help extend the reach of power gating? Mike Muller said during his DAC keynote that the technique looks viable.
Could subthreshold circuitry help extend the reach of power gating? Mike Muller said during his DAC keynote that the technique looks viable.
Could more flexible licensing strategies for cloud-based EDA enable more efficient simulation and a new wave of business models?
Do you know where the IP for your design has been? Or where it’s going? That’s the question a lot of CAD groups face as they struggle with regulatory, bug-fixing and yield issues.
Can process migration tools help the yield-challenged and speed the path to 20nm?
The Silicon Integration Initiative (Si2) is targeting the end of the year for release 2.0 of its OpenDFM standard, which will include support for DRC+ and make it possible to build search engines for yield.
The 20nm node will be making headlines at DAC. What are the challenges, what’s being done about them and how could this work help engineers working at more mature nodes.
Verification drives system-level adoption as sales leap 76%. Virtual prototyping is also on the rise but there are gaps in the tool-set.
What are the chances that FD SOI will become a mainstream process for future nodes?
Blue Pearl is building alliances to bring its timing analysis tools to more users.
At last year’s DAC, leading EDA analyst Gary Smith said chip design had run into a big problem: it was already too expensive to be worthwhile for most companies. Soon afterwards, three companies rang to tell him that the figures were too pessimistic: it was not costing in the region of $75m but perhaps just […]