Making FPGA prototyping easier
In the next couple of days, we’ll be launching a guide overview to FPGA prototyping, so some of the details in today’s (April 2) release of Synopsys’ Synplify 2012.03 immediately caught our attention.
The release covers both the Synplify Pro and Synplify Premier synthesis tools but it’s the latter that now includes a ‘continue-on-error’ feature that allows you to run the complete compile on your FPGA array and receive a report of missing or wrong definitions across the whole design that you then fix as a group, rather than having the compile stop for each bug.
The Premier ‘continue on error’ feature is interesting in a couple of respects.
- It should be quicker than running the compile, stopping at each error, fixing it and then starting again from the beginning.
- It helps to address the knowledge gap facing many ASIC and SoC designers when it comes to handling dedicated FPGA HDL code.
As well as this new feature, Synplify incorporates a datapath latch conversion feature to convert ASIC’s automatically into FPGAs, so you can use the one set of source files across the main design and the prototype.
There’s always the fear that getting your FPGA prototype up and running can just take too long, to the extent that it arrives only just before (and still in some cases after) you’ve got your first silicon.
With SoCs trending towards more software than hardware, not being able to get the software done as quickly as possible is a big deal for time to market and, obviously, profit. You want that software near locked when the silicon arrives.
Beyond that – and particularly for mobile comms – you might want to test the prototype system fairly exhaustively in real-world conditions.
Synopsys doesn’t give a specific benchmark for just how much faster the latest Synplify can make prototyping but, coupled with other new features aimed at generic FPGA synthesis, it lays claim to a 30% improvement in overall runtime.
Some of those other supplements include fault-tolerant error correcting code memories (useful for safety-critical designs), selective triple modular redundancy and Hamming-3 encoding for the detection and correction of soft errors.
Read more here.
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