The downward trend of ASIC design start continues out to at least the middle of the decade as development continues to shift towards ASSPs, according to the latest research from Gartner. However, even combined, design starts are still going down at the rate of 2 to 3 per cent per year, from around 6000 in 2011 to a little over 5000 in 2016.
Gartner says, by 2016, designs for process nodes at 45nm and after will account for 40 per cent of the total, there will still be a sizeable market for designs on 90 and 65nm. The two combined will account for 39 per cent of all chip design starts. In 2011, designs at 45nm or lower represented 13 per cent of total design starts.
Of the current design starts, a large number still represent comparatively low volumes – 41 per cent will generate $2m or less in sales and 29 per cent used fewer than one million gates. Just under a third are estimated to sell more than a million units during their design lifetimes.
Gartner says the emphasis in chip design is shifting to the use of lagging processes rather than advanced and recommends to EDA vendors that they strengthen their offerings for mainstream processes although they will still need to spend big to support the leading-edge process technologies.