emulation

April 30, 2015
Dr Lauro Rizzatti is an independent verification consultant. You can contact him at lauro AT rizzatti DOT com

Putting emulation on the map

Emulation is now served by all three leading vendors and is a hot topic for discussion among engineers. The major verification conferences need to follow suit.
Expert Insight  |  Topics: EDA - ESL, IC Implementation, Verification  |  Tags: , ,   |  Organizations: , ,
January 20, 2015
Veloce2 emulator

Assertion-based emulation

Combining assertion-based verification techniques with emulation makes for easier debug, better coverage and greater functional efficiency.
November 23, 2014
Cadence Palladium cluster

Acceleration homes in on power issues

Emulation and simulation acceleration technologies provide the means to more efficiently detect power issues before tapeout – and find the worst-case modes that need to be fixed.
November 6, 2014
Dr Lauro Rizzatti is an independent verification consultant. You can contact him at lauro AT rizzatti DOT com

The budget case for emulation

Need to convince your FD of emulation’s growing ROI and the need to invest? Click here and ‘Forward’
October 28, 2014
Featured image for hybrid testbench article

Harness virtual machines to create an efficient ‘live’ hybrid testbench

This 'how to' guide shows how to combine the power of emerging and existing technologies for faster, more comprehensive test.
August 19, 2014
ZeBu server

Hybrid emulation for development, validation and verification

This article introduces hybrid emulation, a combination of emulation and virtual prototypes, and its application to tasks such as architecture validation, early software development and software-driven verification.
July 22, 2014
The evolution of software debug using hardware emulation

The evolution of software debug using hardware emulators

We look at how best to leverage both software debug tools and emulators, the limitations to traditional techniques, and the drive toward offline debug.
June 15, 2014
Chips on a wafer

Early tape-out: smart verification or expensive mistake?

Is it worth trying to iron out all the bugs in an SoC before taping out, or should design teams anticipating a re-spin go to silicon earlier and use the chips that come back as verification accelerators?
March 17, 2014
Chris Tice is corporate vice president and general manager of hardware system verification at Cadence Design Systems

The rise of hardware-assisted verification

Verification of hardware and software has become a key bottleneck for chip design. Hardware-assisted verification is removing that bottleneck.
Expert Insight  |  Topics: EDA - Verification  |  Tags: ,   |  Organizations:
January 21, 2014
Cadence Palladium cluster

Productivity, predictability and versatility drive verification environments

Three key characteristics determine a verification platform's ability to add value to the design flow. But how they score within a project depend on how each is applied and at which point.
Article  |  Topics: EDA - Verification  |  Tags: , , ,   |  Organizations:

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