How you can decide what level of DRC you need when you need it
Using on-demand rule checks during place-and-route boosts efficiency and design quality.
IP Integration
Getting the most out of IP based FPGA design with Synplify
How Synplify makes it easier to use IP in FPGA-based designs, and package your own IP for secure reuse, on Altera and Xilinx devices
Using HAPS to streamline IP to SoC integration
The HAPS prototyping system can help designers integrate IP into SoCs more quickly.
Consistency key to gaining the advantages of IP integration
Consistency is vital to IP integration strategies that rely on developing an SoC using a hierarchy of FPGA-based prototypes.
The new semiconductor ecosystem: wants and needs
Leading chip design analyst Gary Smith charts the course through the main questions dominating DAC 2011.
IP hardens up again
Richard Goering System-on-chip designers who work with third-party silicon intellectual property (IP) will see some significant changes at 32nm and below. Physical IP will be highly optimized to specific processes, following intense collaborations between large IP providers and foundries. Processor IP may become less synthesizable and make more use of hard macros. On the plus […]
Taking a broad view
The IEEE Council for EDA has opened its website at www.c-eda.org. Earlier this fall, the IEEE Council for Electronic Design Automation (CEDA) took on formal existence with the election of its first officers. Design consultant and one time DAC general chair Alfred Dunlop is its launch president. He sets out why this is a great […]
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