April 24, 2020
Learn how the latest design for test innovations deliver efficiency and profitability across the design flow.
December 29, 2015
Behind the drivers for memory BIST innovation in areas such as power-on self-test, destructive and non-destructive techniques, and faster memory repair.
August 18, 2012
Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong?
January 24, 2012
The inherent complexity of today’s system-on-chips, with their multiple clock and voltage domains, requires test considerations to be moved further up design flows. The article describes strategies for and benefits from apply test before RTL goes through synthesis, augmenting what is already achieved through memory built-in self test and automatic test pattern generation.