Doc Formal: My 10 golden rules
Ashish Darbari sets out the fundamental qualities of a successful formal verification project.
EDA
How hardware emulation helps drones take flight
In an exclusive interview, Lauro Rizzatti discusses the increasing verification challenges for drone SoCs with Bo Shen, founder of fabless specialist Artosyn.
A better way to merge design files for physical verification
Still using custom layout or place and route tools here? Ditch that time-consuming practice for a real database merge flow.
Driving 4K smartphone and AR/VR device displays
How to combine a display processing unit from one company and a MIPI Display Serial Interface solution from another to build 4K embedded displays for smartphones and AR/VR devices.
How to achieve more accurate NAND soft-bit error injection
The article describes a pre-silicon strategy for the design and verification of SSD controllers that is faster and more flexible than ICE using physical NAND on a daughter-card.
Tackling the design challenges of PCIe 5.0
Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.
Optimizing power and performance trade-offs in CNN implementations for embedded vision
High-performance vision-processing algorithms need optimized CNN engines to deliver the right performance within the power budget of embedded applications.
Doc Formal: Living verification in the fast lane
Why is formal verification not getting the traction it should. The good doctor has some thoughts on that... and a new solution.
Bringing AI into our lives
Using specialised processors to implement key AI computation tasks such as CNNs.
Design space exploration finds hotspots during early process development
A new technique has been developed to catch potential new lithography issues when little design data is available for incoming nodes.