X propagation within RTL simulations can hide fatal bugs. Uncovering and eliminating the effect improves design quality and avoids respins.
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Accounting for on-chip variation (OCV) has become a critical factor in assuring timing closure for nanometer-scale ICs and avoiding over-pessimistic margins.
IEEE 1801-2013 updates and refines the Unified Power Format for low-power VLSI design, reflecting changes in power modeling and verification.
Real-valued modelling provides a way of speeding up the simulation of SoCs with significant analog content through the use of discrete-event solvers.
The technique enables early software development and hardware/software co-design strategies before a project is more rigidly defined in RTL.
Yocto is a project that aims to provide the open source building blocks necessary for custom embedded Linux implementations
A guide to emerging 3D integration techniques for ICs, including a look at various approaches, and some of the tools and standards issues involved.
For a growing number of applications, leakage is a major component of the lifetime energy consumption of an MCU, making it essential to shut the processor core down when it is not needed. Sleep modes help control that.
A side-channel attack is a form of reverse engineering that takes advantage of the information leakage from electronic circuitry. And it is a major risk to design security.
The value of the emulation market has almost doubled in the last four years as the technique becomes increasingly valuable to hardware/software co-verification.
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