March 1, 2008

The veteran competitor

In his early days in the semiconductor industry, Morris Chang Morris Chang was one of the “non-Texans” to Texas Instruments and was a manager struggling with the question of how to get individual transistor yields to somewhere around three or even four per cent. One of his colleagues – another immigrant to the Lone Star […]

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December 1, 2007

Portable multimedia SoC design: a global challenge

Today more than ever, the difference between design success and failure resides in engineers’ ability to master all critical design factors at once. Meanwhile, systems-on-chip (SoCs) represent a multidisciplinary challenge that spans the entire flow from architecture through design to test and finally mass production. For portable applications in particular, SoCs present especially stringent constraints […]

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September 1, 2007

Characterizing process variation in nanometer CMOS

The correlation of a statistical analysis tool to hardware depends on the accuracy of underlying variation models. The models should represent actual process behavior as measured in silicon. This paper presents an overview of test structures for characterizing statistical variation of process parameters. It discusses the test structure design and characterization strategy for calibrating random […]

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June 1, 2007

Implementation of a DFM checker for 65nm and beyond

Design for manufacturing (DFM) sign-off is a required step in most deep sub-micron technology design environments. However, there is no common methodology for DFM sign-off. We believe DFM should not only give an estimate of the yield, but should also point out where failures are most likely to occur, and where designers can improve their […]

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March 1, 2007

Confronting chip assembly challenges

Until recently, hierarchical design flows have been favored for the implementation of multi-million gate SOCs. However the rapid increases in design size brought on by nanometer process geometries have seen engineers seek to cope with the inherently block-based nature of such flows by seeking greater concurrency between the block implementation and chip assembly stages in […]

March 1, 2007

Scan infrastructure and environment for enhanced at-speed ATPG

A major issue faced by SoC design teams adopting 90nm and 65nm process nodes is the increase in yield fall-out. At 90nm it is estimated that 30% of yield fall-out is due to performance and signal integrity issues. As a result, accurate and cost effective at-speed manufacturing test and characterization has become evermore critical to […]

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December 1, 2006

Leakage power optimization for a wireless comms SoC

Leakage has become a critical concern for sub-100nm silicon process technologies. It had started to become a significant factor in a chip’s overall power profile at 130nm, but by 90nm things had worsened with leakage accounting for perhaps 30% of a chip’s total power consumption. At 65nm, leakage represents more than 50% of power consumption. […]

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September 1, 2006

Advanced post-silicon verification and debug

More than 50% of highly complex systems-on-chip (SoCs) have functional issues at first silicon, issues that emerge after engineers have spent much time and money on verification and emulation. These issues delay time-to-ramp and cause significant losses of direct and indirect product revenue. All this demonstrates the need for efficient post-silicon debug methodologies and tools. […]

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September 1, 2006

Visibility enhancement for full-chip simulation

The most expensive parts of today’s system-on-chip (SoC) design flow are where engineers must engage in direct manual effort or expend their energy making decisions. Unfortunately, far too much time and money are wasted on tasks that do not add value — such as trying to figure out if supposedly correct intellectual property (IP) is […]

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June 1, 2006

Design and manufacturing unite to tackle process variability

Analyses made by semiconductor manufacturers have demonstrated that maintaining pattern fidelity is critical, and that this task faces increasing limitations at the 65nm process node and below. At these technology nodes, even the most advanced resolution enhancement technologies (RET) have a difficult time with certain layout topologies.  When the impact of this is observed across […]

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