2D tools adapt to create smaller monolithic 3DIC designs

By Chris Edwards |  No Comments  |  Posted: June 9, 2016
Topics/Categories: Blog - EDA, IP  |  Tags: , , , ,  | Organizations:

Researchers at the Georgia Institute of Technology adapted conventional 2D layout tools to a two-layer monolithic 3D process that resulted in sizeable space and power savings.

“We call it Shrunk-2D,” said Professor Sung Kyu Lim, director of the Georgia Tech Computer Aided Design Laboratory at the Design Automation Conference in Austin, TX on Wednesday (June 8). “Everything is made 50 per cent smaller and then we do a place and route. And it really works: it gives us a design that outperforms 2D.”

The technique shrinks the area consumption of standard cells by changing them to double-decker structures. This avoids the need to treat the layers of the monolithic as fully independent, which would demand a different, and currently unsupported approach to place and route. As well as adapting a conventional place-and-route flow based on Cadence Design Systems’ Innovus, the team used Synopsys PrimeTime with some alterations to perform timing analysis for the two-tier structures.

ARM processors used in test

The Georgia team used processor IP from ARM to evaluate the performance of the adapted tools and the monolithic 3D technology. “We wanted to see the benefit of using monolithic 3D with real PDKs and real IPs,” Lim said.

“We have done seven designs in 2D and 3D. We then swept the frequency to see what the benefits are. We found the power benefit of monolithic 3D over 2D was more at 28nm than at 7nm. But as your clock frequency increases you get more power savings,” Lim said, largely because the area reductions results in the use of fewer buffers for longer interconnects.

The overall wire-length saving was 20 to 25 per cent for the designs performed by the Georgia Tech team. “The wire-length savings were regardless of the technology node.”

Lim noted that total cell area reductions ranged from 3 and 15 per cent, increasing with clock frequency largely because of the reduction in buffer count.

3DIC tradeoffs

The monolithic 3D processes will demand some tradeoffs that are not seen in 2D, Lim said. “We found something interesting that we didn’t see so much with planar: pin capacitance may get in the way with finFET devices.”

Because of the area reductions, wire capacitance tends to reduce but pin capacitance within the cells remains constant, making it a more prominent parasitic effect.

The cell-area reductions tended to improve with higher target frequency the research found. The use of smaller gates on finFET processes and other cell-level optimizations might improve the pin capacitance, Lim noted.

Leave a Comment

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors