A look at the ways in which the I2C serial interface specification is being updated to form I3C, and its use in sensor subsystems
By taking a pragmatic approach, the two technology giants have comfortably adopted high-level synthesis and verification - and have shared their experiences.
A look at three design challenges for USB Type-C: implementing two SuperSpeed datapaths on a reversible connector; partitioning the design to support multiple USB Type-C variants; and partitioning the management software.
A look at USB 3.1, which offers data rates of up to 10Gbit/s, and the way that the USB 3.1 protocol has changed to support this rate.
An analysis of what it takes to build true random number generators that can provide a strong cryptographic basis for systems security, especially for IoT devices.
A quick look at Bluetooth Smart and how it can be used to provide network connections in certain classes of IoT application.
Flash is the ice cream of memory technologies - everybody loves it. But you need to build the right verification environment to extract the greatest benefit.
How to work with multiple levels of physical hierarchy when floorplanning multicore, multiport, multi-million gate SoCs
Advances in RTL floorplanning help cut front-to-back-end iterations, speed synthesis by 10X and boast the capacity needed for today's designs.
How to ease AMS verification using tools that improve simulation debug, ease IP integration, and speed design analysis and centering
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