Using USB Type-C connectors to combine both USB-C 3.1 and DisplayPort data streams, to support data, audio, video and power connections on a single port
High level synthesis (HLS) was adopted to realize innovative display IP as developed by a small core engineering team.
Using VESA's Display Stream Compression (DSC) standard to enable visually lossless performance and low latency for ultra-high-definition displays.
CCIX is a cache coherency protocol, based on PCI Express, for interconnecting high-performance heterogenous multiprocessing systems.
Quadrupling the performance of a dedicated CNN engine within an embedded vision processing core brings more complex graph processing within reach.
SoC developers who want to use USB Type-C in their designs will have to implement HDCP 2.2 content protection so that the target devices will be able to play protected content.
The increasing complexity of human-machine interfaces is challenging processor designers to produce the necessary performance within a limited power budget
The rising bandwidth demands of data centres have driven the development of 25G Ethernet, which will also form a pathway to 100G.
Using deep learning techniques and convolutional neural networks to bring facial recognition capabilities to embedded systems.
Addressing the challenge of achieving ASIL D certification of the functional safety of an SoC for use in the safety-critical path of an automotive system.
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