September 16, 2013
A first look at the role of the protocol layer in USB 3.0.
September 16, 2013
A look at the USB 3.0 functional layer, an application layer and system software on the host side, and a logical function and device on the device side.
September 16, 2013
A look at the role of four types of transaction in the USB 3.0 protocol layer: bulk, control, interrupt and isochronous.
September 16, 2013
A look at the USB 3.0 physical layer, including the PHY and the physical connection between two ports, which is carried on two differential data pairs.
August 25, 2013
What ARM learnt when it ran a Mali GPU-based test chip through a Synopsys tool flow onto a TSMC 20nm process
July 25, 2013
Formal verification techniques are becoming more widely used as the size and complexity of SoCs and increases.
July 19, 2013
How Cisco eliminated iterations in the ASIC handoff of a gigahertz networking chip by using physically aware synthesis
July 3, 2013
Clock domain crossing bugs undermine the productivity gains of moving to block-based design, but can be tackled through hierarchical formal analysis.
May 14, 2013
RTL sign-off strategies ease SoC design and IP integration by enabling early analysis and optimization of CDC, power, X propagation, timing, and resetability issues.
April 24, 2013
Many problems arise during the IP-to-SoC phase of FPGA-based prototyping due to the mix-and-match nature of the prototypes not the actual designs.