EDA Topics

June 1, 2007

Shadow model and coverage driven processor verification using SystemVerilog

This paper describes a random test generation strategy we are using to complement the verification of upcoming generations of processor. SystemVerilog provided the means to define the functional coverage of our design and to employ the shadow modeling technique, significantly improving our verification flow. Shadow modeling is a reliable method for proving the functionality of […]

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June 1, 2007

Share and share alike

For a design targeted at the 130nm process node or below, the cost of a dedicated mask-set is getting brutal. At 130nm itself, a semiconductor company is likely to pay between $500,000 and $600,000 per set. That price tag rises to around $1m at 90nm, and to $1.5m at 65nm(Figure 2). One recent forecast for […]

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June 1, 2007

A pragmatic approach to evaluating NoC strategies

Network-on-chip (NoC) could prove to be an effective methodology that addresses interconnect roadblocks to the development of more complex systems-on-chip. However the term covers many approaches, some of which – simple enhancement to existing bus technologies, the costly adaptation of theoretical networking concepts – fall short either in terms of performance or NREs. The article […]

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March 1, 2007

Consumer market promises steady progress

US factory-to-dealer sales of consumer electronics will surpass $155B in 2007, representing 7% growth, according to the most recent forecast from the Consumer Electronics Association. This performance will follow on from an expected $145B market in 2006, a year which surpassed even the most optimistic forecasts by logging growth of 13%. “The industry outlook is […]

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March 1, 2007

Double figures for DATE

DATE 07 (April 16-20) marks an important milestone for the Design Automation and Test in Europe conference as it reaches its tenth edition. As we went to press, the main technical program was still being finalized, but DATE has again received record submissions, 933 against last year’s 834. The most obvious change in 2007 is […]

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March 1, 2007

Electronic system level design for embedded systems

There is a growing productivity gap in the design of embedded systems. One recent survey estimated that the number of lines of embedded code written per year is growing at a rate of 46% a year, although the number of developers available to write it is growing at only 7.5%. The problem is further compounded […]

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March 1, 2007

From A to B via Z

How important is it that the history of electronics is passed on from generation to generation of engineers in the ‘right’ way. OK, let’s acknowledge that, as in war, history is always dominated by the victors, not the losers. Let’s also admit that anyone with a career in this business wants its image to be […]

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March 1, 2007

MPSoC demands system-level design automation

The relative performance of a single processor has leveled off in the last decade. Built-in instruction-level parallelism is becoming less efficient because issuing more than four instructions in parallel has little effect on most applications. Meanwhile, recent attempts to boost performance have come dangerously close to the energy/power consumption ceiling. Dedicated hardware accelerators may prove […]

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March 1, 2007

Re-evaluating the flow for package-aware chip design

Chip and package design are all too often still seen as separate stages in the design process. In today’s nanometer age and with the growing use of techniques such as system-in-package, this lack of integration can have catastrophic results. Package designers frequently encounter overly complex and un-routable silicon that requires multiple iterations to fix. Problems […]

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March 1, 2007

Revealing the hidden cost of performance for physical verification

The increasingly onerous nature of physical verification at today’s nanometer process geometries requires the regular benchmarking of appropriate tools, if designs are to be realized in a cost-effective manner. However, the criteria for such benchmarking are all too often limited to relatively simplistic notions of ‘performance’. The article explains that the real cost of physical […]

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