Consumer electronics is a difficult business.Market windows open and close quickly. Cost is critical. Requirements change unpredictably. Risk is high. Functionality and performance increase with every product generation, while both manufacturing-limitations and feature-driven demand require low power implementations. Of all these, power constraints have the largest impact on current product architectures. As CMOS reaches its […]
Timing closure is one of the major problems faced by SoC designers. The inclusion of several, often diverse, IP cores that need to communicate with each other on a chip makes it difficult for a designer to meet the complex timing requirements between these cores. Furthermore, as process nodes shrink, process variability becomes a more […]
In late 2001, Nick Baker and other members of the Ultimate TV team at Microsoft learned that the company was ending development work on the product. For a still youthful engineer whose curriculum vitae already took in some ill-fated early-days video card work at Apple and the short-lived 3DO games console, Baker could have been […]
What do we mean by a ‘left shift’ in design for manufacturing (DFM) analysis? Think of it as moving the DFM analysis from a tool run by the manufacturer into an integrated solution within the printed circuit board (PCB) design system. It is a major advance in the design of PCBs, allowing users to ultimately […]
Applications ranging from gaming to digital media to data analytics continue to grow more complex and constantly demand increasing computing power from computer systems. Historic growth in microprocessor performance has primarily been responsible for assuring a steady growth in the computing power of computer systems. Traditionally, this growing performance has been sustained by scaling down […]
More than 50% of highly complex systems-on-chip (SoCs) have functional issues at first silicon, issues that emerge after engineers have spent much time and money on verification and emulation. These issues delay time-to-ramp and cause significant losses of direct and indirect product revenue. All this demonstrates the need for efficient post-silicon debug methodologies and tools. […]
The most expensive parts of today’s system-on-chip (SoC) design flow are where engineers must engage in direct manual effort or expend their energy making decisions. Unfortunately, far too much time and money are wasted on tasks that do not add value — such as trying to figure out if supposedly correct intellectual property (IP) is […]
Introduction Complete system-on-chip (SoC) design assembly, configuration and verification environments emerged in the 1990s to address an increasing design gap between the capacity of silicon and the ability of engineering teams to fill that gap meaningfully with optimized system designs. Despite the need being addressed by these early environments, adoption was slow. In this context, […]
Up to 80% of the overall design cycle time can today be spent on verification. Constrained-random testing (CRT) was developed in response to greatly reduce the amount of code needed to create a verification environment. However, CRT-based methodologies that do not include functional coverage are analogous to shooting blind [1]. Functional coverage provides essential feedback […]
The increased size and complexity of designs continues to push design and verification methodologies to progressively higher levels of abstraction. These upward shifts in abstraction tend to occur about every decade or so, and we are currently experiencing one in the shift from RTL to transaction-level modeling (TLM). Abstractions must eventually be converted back effectively […]