EDA Topics

March 1, 2007

Double figures for DATE

DATE 07 (April 16-20) marks an important milestone for the Design Automation and Test in Europe conference as it reaches its tenth edition. As we went to press, the main technical program was still being finalized, but DATE has again received record submissions, 933 against last year’s 834. The most obvious change in 2007 is […]

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March 1, 2007

Electronic system level design for embedded systems

There is a growing productivity gap in the design of embedded systems. One recent survey estimated that the number of lines of embedded code written per year is growing at a rate of 46% a year, although the number of developers available to write it is growing at only 7.5%. The problem is further compounded […]

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March 1, 2007

System-level design matures

How do we bridge the gap between the highly abstract view provided by traditional system-level design and the detailed implementation in RTL? The article answers this question by describing the components within an ESL methodology and illustrating its use via customer case studies. The methodology uses the ARM RealView SoC Designer tool and Tenison Design […]

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March 1, 2007

Consumer market promises steady progress

US factory-to-dealer sales of consumer electronics will surpass $155B in 2007, representing 7% growth, according to the most recent forecast from the Consumer Electronics Association. This performance will follow on from an expected $145B market in 2006, a year which surpassed even the most optimistic forecasts by logging growth of 13%. “The industry outlook is […]

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March 1, 2007

Build vs buy in an SoC world

We are now entering the tail end of an era, and many of us do not even know it. For as long as there have been microprocessors, there have been engineers and engineering teams whose job it was to create interconnects. Although this will undoubtedly continue in some companies, the increasing complexity of systems-on-a-chip (SoCs) […]

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March 1, 2007

MPSoC demands system-level design automation

The relative performance of a single processor has leveled off in the last decade. Built-in instruction-level parallelism is becoming less efficient because issuing more than four instructions in parallel has little effect on most applications. Meanwhile, recent attempts to boost performance have come dangerously close to the energy/power consumption ceiling. Dedicated hardware accelerators may prove […]

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March 1, 2007

Re-evaluating the flow for package-aware chip design

Chip and package design are all too often still seen as separate stages in the design process. In today’s nanometer age and with the growing use of techniques such as system-in-package, this lack of integration can have catastrophic results. Package designers frequently encounter overly complex and un-routable silicon that requires multiple iterations to fix. Problems […]

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December 1, 2006

Leakage power optimization for a wireless comms SoC

Leakage has become a critical concern for sub-100nm silicon process technologies. It had started to become a significant factor in a chip’s overall power profile at 130nm, but by 90nm things had worsened with leakage accounting for perhaps 30% of a chip’s total power consumption. At 65nm, leakage represents more than 50% of power consumption. […]

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December 1, 2006

Common pitfalls in PCI Express design

PCI Express is a point-to-point communications interface. It is neither an evolved nor enhanced form of PCI or PCI-X, but, essentially, a high speed, low voltage, differential serial pathway for communication between two devices, although it uses the same programming model as its predecessors. It employs a protocol that allows devices to communicate simultaneously by […]

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December 1, 2006

Design of SoG with p-SI TFTs using AMS simulation for AMOLEDs

The use of poly-Si TFTs for active matrix OLEDs (AMOLEDs) allows peripheral circuits to be integrated on a glass substrate at low cost and reduces the number of external driver ICs. The prospect of such integration means it is likely that emerging system-on-glass (SOG) design projects will feature both analog and digital blocks, such as […]

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