Companies and mask shops already have plans and policies to secure the storage and transmission of sensitive layout VLSI data. These include confidentiality and non-disclosure agreements, and encryption. However, traditional VLSI file formats such as GDSII never popularized the type of constructs that facilitate intellectual property (IP) protection. The OASIS format does have these constructs. […]
Nanometer scaling severely inhibits the path to achieve sustainable yield. In response more responsibility for forecasting potential failures must shift to design for manufacturing (DFM) methodologies that can be applied early in the design process. Yet, while these hold much promise, manufacturing test and failure analysis remains at the forefront of determining why chips fail. […]
The IEEE Council for EDA has opened its website at www.c-eda.org. Earlier this fall, the IEEE Council for Electronic Design Automation (CEDA) took on formal existence with the election of its first officers. Design consultant and one time DAC general chair Alfred Dunlop is its launch president. He sets out why this is a great […]
Introduction Selecting the proper ADC can appear a formidable task, considering the thousands on the market. A direct approach is to go to the selection guides and parametric search engines. Enter the sampling rate, resolution, power supply voltage, and other properties. Click ‘find’. And hope for the best. But it’s usually not enough. How does […]
Semiconductor devices are being fabricated with features that are less than half the wavelength of the available lithography exposure tools. Increasing circuit density has improved the complexity and performance of ICs but also led to serious patterning proximity effects. These effects make the chips almost impossible to fabricate without optical proximity correction (OPC) technology. Thus, […]
Major yield-Inhibiting Issues At each successive process node, additional defect mechanisms appear and hinder the ability to achieve desired yield (Figure 1). The trend toward declining yields has led to a resurgence in the application of design for manufacturing (DFM) methodologies.Much of this reinvigorated effort relies heavily on a new breed of tools and technologies. […]
The network-on-chip (NoC) design paradigm is seen as a way of enabling the integration of an exceedingly high number of computational and storage blocks in a single chip. But its adoption and practical implementation face important and unsolved issues related to design methodologies, test strategies, and dedicated CAD tools. The System-on-a-Chip Research Lab at the […]
Design teams are becoming increasingly concerned at the growing disparity between the capacity of silicon in the latest processes and the design and verification capabilities of simulation tools. A number of trends are now converging to enable a step function increase in verification to complement and extend the debug and verification capabilities of HDL simulators. […]
The efficient management and synchronization of design data is now a necessity and no longer something that is a ‘nice-to-have’. Design complexity continues to increase with one result being that development spreads across several groups (often in different places). A project may also have several thousands design files generated by various tools from different vendors […]
If one thing has become clear as process geometries have gone below one micron, it is that the traditional development model is broken. It seems only recently that companies were talking about adopting a greater ‘customer focus’, but even the linear sequence of first, finding out what the client wants; second, getting your designers to […]
