Verification has become one of the main bottlenecks in hardware and system design. Several verification languages, methods and tools addressing different issues in the process have been developed by EDA vendors in recent years. This paper takes the industrial user’s point of view to explore the difficulties posed when introducing new verification methods into ‘naturally […]
We have entered the era of the multi-processor system-on-chip (MPSoC) but it remains a major frustration that, for a technology that is so imminent and so necessary, there is as yet no real vision out there that goes beyond the parochial. Yes, ‘point’ issues are also being addressed, but we need to define the concept, […]
There must be a better way to keep track of electronic engineering software licenses. EDA tools are very expensive, essential to R&D work, and must be properly maintained to ensure that commercial designs are completed on-schedule. Nevertheless, companies traditionally set aside little management time to put formal control systems in place for these assets. Consider […]
Concurrent multi-corner, multi-mode analysis and optimization is becoming increasingly necessary for sub-65nm designs. Traditional P&R tools force the designers to pick one or two mode corner scenarios due to inherent architectural limitations. As an example of the problem, a cellphone chip typically needs to be designed for 20 mode/corners scenarios. In the absence of a […]
The paper outlines the criteria upon which an OEM should make its selection of a third-party PCB design supplier. It groups these into three main categories. Staff with appropriate technical and communications skills. Comprehensive and fully documented design processes (ranging from the use of consistent design strategies to approaches to component library maintenance). Tool support […]
Simultaneous Switching Noise (SSN) is the voltage fluctuation caused by the simultaneous switching of groups of output chip I/O drivers that drive high slew rate signals. It has an impact on I/O and core power supply lines and on signal lines, and is an increasingly important challenge for designs that incorporate high performance interfaces, such […]
Network-on-chip (NoC) could prove to be an effective methodology that addresses interconnect roadblocks to the development of more complex systems-on-chip. However the term covers many approaches, some of which – simple enhancement to existing bus technologies, the costly adaptation of theoretical networking concepts – fall short either in terms of performance or NREs. The article […]
Today, most SoC designs include both digital and analog components on the same chip, taking advantage of nanometer geometries. This demands that the current design flow bottleneck due to analog verifi-cation and integration is addressed in ways that enable this process to be completed both thoroughly and efficiently. SPICE simulation was accurate but slow and […]
Some 161 papers will feature during this year’s 44th Design Automation Conference (June 4-8) in San Diego with four strands at the forefront. System-level design (ESL), design for manufacturing/yield (DFM/DFY), low-power design and verification accounted for more than 40% of submissions this year, and the final line-up represents these topics in broadly similar proportion. For […]
When I left the semiconductor industry to become an EDA Analyst, I was struck by two things. The first was the professionalism of the PR firms handling the EDA accounts. They not only did jobs that would be expected of them by silicon vendors, but also performed functions that we would consider part of a […]
