Productivity levels for hardware design, specification, simulation and validation have been raised by the formal approval of IEEE 1800 SystemVerilog as an industry standard. Evolved from the Verilog hardware description language, SystemVerilog is now the language of choice for developing verification and design intellectual property (IP). As a result, EDA companies are progressing rapidly in […]
Designers thinking about low power and energy have a variety of strategies at their disposal. The most common are: Process/libraries (e.g. low-power processes/libraries; high and low threshold voltage cells; and voltage scaling); Power and voltage domains; Clock gating; Low-power optimized clock synthesis; Low-power synthesis (e.g. automatic insertion of operand isolation circuitry); Implementation optimizations (e.g. operand […]
When migrating from FPGA prototype to ASIC, engineers need to interface with multiple silicon and software vendors. Designing with FPGAs often requires the use of several software platforms, including front-end synthesis tools, FPGA software development tools, and verification and timing analysis tools. Migrating to an ASIC platform involves using a parallel design flow with different […]
Why are more chips late to market and cost three times more to design at 90-nanometer (nm) than at 130nm? Today’s ASSPs and ASICs are huge, approaching one billion transistors, with clock speeds exceeding 1-GHz. Engineers struggle to manage the complexity of devices that achieve these levels of performance and size. A natural reaction to […]
Ellen Sentovich As EDA Tech Forum went to press, the programme for 2006’s Design Automation Conference (July 24-28) in San Francisco was only just being made public. However, one thing was already clear. The event is set to be bigger than ever before. “We had been concerned about the move to July because of the […]
Engineers on the leading edge of nanometer design are dealing with physical effects that change the way mixed-signal ICs are verified – in timing, power, reliability and yield. With the IC verification effort accounting for 60-80% of the development cycle, choosing and deploying the right mixed-signal verification solution can significantly improve productivity and the return […]
Analyses made by semiconductor manufacturers have demonstrated that maintaining pattern fidelity is critical, and that this task faces increasing limitations at the 65nm process node and below. At these technology nodes, even the most advanced resolution enhancement technologies (RET) have a difficult time with certain layout topologies. When the impact of this is observed across […]
Introduction The emergence of the SystemVerilog and PSL assertion languages promises to improve the effectiveness of existing verification flows. First, assertions give better local observability of the functionality they represent. Second, the assertions augment the textual specification to provide a more formal, executable representation of the functionality. Third, since the assertion languages have common semantics […]
DATE 06 (March 6-10) is the ninth edition of the Design Automation and Test in Europe conference and the organizers have again received a record number of submissions, this year 834. This reflects the fact that today DATE is not merely a European conference but has become a well-known global event, receiving paper proposals and […]
For years, ASIC and FPGA designers have shared the goal of having totally reusable intellectual property (IP) blocks. This goal has been partially fulfilled, with the introduction of high-level hardware description languages such as VHDL and Verilog, and powerful Register Transfer Level (RTL) synthesis tools in the late 1980s and early 1990s. However, with a […]
