SystemVerilog, the standard that originated from Accellera and is now IEEE1800, is not just for Verilog users. VHDL users can also improve their design processes using its proven verification features. Anyone involved in systemon- chip (SoC) design may face a mixed-language environment and will appreciate being able to leverage SystemVerilog with the VHDL portions of […]
Cswitch’s CS90 Configurable Switch Array device has an interconnect structure, the dataCrossconnect network, that delivers bandwidth at 40- 100Gbps for packet-based applications. For packet handling tasks, the chip includes embedded configurable blocks, Configurable Packet Engines, that support functions such as frame parsing, CRC and hashing, and fast address look-ups, all at up to 1GHz. For […]
Electronic system level (ESL) design is moving to a new stage in its development, advancing from a proof-of-concept environment to one that is seeing its adoption and deployment at the forefront of design. The article terms this shift ‘ESL 2.0’. The reason for this goes beyond mere marketing hype. Inherent in the transition defined above […]
The headline number in the Consumer Electronics Association’s (CEA) latest market forecast contained a few devils in the detail, although the sector does seem poised to defy more pessimistic views of the economy’s prospects. The projection of 6.1% growth for 2008 is robust, giving just over $171bn in US factory door sales (Figure 1).Meanwhile, GDP […]
Although no EDA company counts among its membership (for good practical reasons), it is fair to describe the US Consumer Electronics Association (CEA) as one of technology’s most broadly representative trade bodies. From retailers and brand holders to the hardware and software companies that directly supply components for CE products, the CEA has a position […]
This year’s general chair of Design Automation and Test in Europe is Donatella Sciuto, a full professor at the Politecnico d iMilano in Milan, Italy. She received her Laurea in Electronic Engineering from the Politecnico di Milano in 1984 and her PhD in Electrical and Computer Engineering in 1988 from the University of Colorado, Boulder. […]
Changes in defect distribution, increasing design complexity and pressures from the specialist I/O and packaging arenas are creating a dilemma during component test. On the one hand, the generation of more test patterns would appear to be necessary; but on the other, fewer test ports are available. The article describes a strategy for addressing this […]
Today more than ever, the difference between design success and failure resides in engineers’ ability to master all critical design factors at once. Meanwhile, systems-on-chip (SoCs) represent a multidisciplinary challenge that spans the entire flow from architecture through design to test and finally mass production. For portable applications in particular, SoCs present especially stringent constraints […]
The article describes and illustrates, by way of a case study, an innovative approach to functional verification. It enables the reuse of test patterns through the coordinated combination of a top-level testbench and subordinate testbench modules. It is based on a new add-on tool, VTrac+, that extends Mentor Graphics’ ModelSim/Questa software to stimulate, compare and […]
For simulation to correctly predict silicon behavior, the logic implementing a design should adhere to the setup and hold constraints specified for clocked elements. However, with multiple asynchronous clocks on a single chip driving logic, designers cannot help but violate setup and hold constraints. This causes metastability, which in its turn leads to non-deterministic delays […]