Hierarchical signoff of SoC designs at advanced process nodes
Hierarchical signoff strategies for large SoCs at advanced nodes can be effective if sufficient attention is paid to reflecting the impact of cross-hierarchy parasitics.
EDA
Six ways to exploit the advantages of finFETs
FinFET processes and libraries are maturing, enabling designers to explore the best ways to take advantage of the capabilities of the new transistor design
Implementing DDR DRAM in automotive applications
A look at how DDR DRAM is being adapted for use in automotive systems, and the demands its use puts upon interface IP for SoCs.
How functional safety verification helps us build safer cars
Considering the issue of functional safety verification in automotive systems design, within the context of ISO26262
Best practice in scan pattern ordering for test and diagnosis
How to tune your scan pattern creation and application to cost-effectively match your test objectives.
Exploring the advantages of monolithic Bluetooth low energy radio integration
A look at implementing Bluetooth low energy interfaces into a design and the trade-offs involved in making different levels of integration
Taking risk out of software-driven networking SoCs
How virtualization and integration with hardware testers are enabling networking SoCs in the billion-gate era.
Wally Rhines separates the signal from the noise
Mentor's chairman and CEO has dug into why chip sales forecasts often miss the target and suggests some tools for assessing the Internet of Things.
How place and route is adapting to challenges below 10nm
Multi-patterning, finFETs and more are forcing more detailed overhauls of P&R software at each process node. We dig into some of the key new issues and how they are being addressed.
The challenges of automotive functional safety verification
Engineers developing an SoC for the automotive market have to show that it doesn’t have functional safety issues - even if the SoC enters an unexpected state. Here's how to tackle the safety verification task.