The ETSOI strikes back

By Chris Edwards |  1 Comment  |  Posted: June 14, 2012
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A day ahead of Intel’s VLSI Technology Symposium paper on its 22nm finFET process, a group led by IBM set out to show that silicon-on-insulator (SOI) devices could do as well not only on low-power, where SOI has traditionally had the edge, but high-performance circuits.

The comparison is not entirely apples to apples: Intel describes a production process on Thursday whereas Ali Khakifirooz, lead device engineer at IBM, described in his Wednesday slot what is currently a lab-based device. It uses a thicker insulator and a wider pitch – 100nm – than would be used in final products. However, Khakifirooz argued that the thicker 100nm buried oxide insulator worsened self-heating – production devices using a 25nm buried oxide would suffer less and deliver higher current – and that the effects of strain would be more pronounced in narrower, production-ready transistors. Despite the caveats, the drive current levels he described were way above what we have become used to from fully depleted (FD) or, as IBM terms it, extremely thin (ET) SOI devices. The drive current at the high-performance end is more characteristic of a bulk CMOS process.

“High-performance devices don’t benefit as much from a steep subthreshold slope [which SOI provides] as low-power. They benefit from better transport,” said Khakifirooz.

Earlier in the day, Siméon Morvan of the research institute CEA-Leti, described how the team of which he was a member used strained SOI to push the NMOS drive current for an experimental 14nm device to 1148µA/µm. Without strain, FD-SOI devices demonstrated performance in the 800-900µA/µm range when presented at the 2010 International Electron Device Meeting (IEDM), by CEA-Leti, and the VLSI Technology Symposium last year, by IBM.

Closing the FD-SOI session at the symposium, Khakifirooz described how the IBM 22nm device surpassed that – pushing all the way out to 1600µA/µm for NMOS – using a different mix of strain techniques.

“The Ion result I would say is better than the 32nm [bulk] devices that have been recorded and it matches the data being presented tomorrow,” said Khakifirooz, referring to Intel’s finFET paper.

Both SOI papers demonstrated that strain is viable for FD-SOI, including one technique that was not expected to work so well: silicon germanium in the PMOS channel. It’s hard to put a layer of silicon germanium under a silicon channel to provide compressive strain when the layer you have to play with is 6nm thick and sitting on top of a silicon dioxide layer.

So, the IBM team took the approach of condensing germanium into the thin layer of silicon to make a silicon germanium channel – with 23 per cent germanium. “You get what you get,” said Khakifirooz when asked why 23 per cent.

For the PMOS device, the IBM team also focused on the contact area. “As you scale the device pitch down the contact takes a larger proportion of the device area. So stress coupling from that becomes much stronger. We achieved a 25 per cent increase in drive current using contact stress,” said Khakifirooz. The net result was a PMOS device with a drive current of 1250µA/µm.

For the NMOS transistor more conventional channel-based strain techniques were used even though conventional wisdom is that short-channel devices would not see much benefit. Applied to long-channel devices, strained SOI yielded a 70 per cent increase in drive current. This fell to 27 per cent in the target device, but this was still a usable result that helped push performance up. Using a different epitaxy process to lower external resistance, the performance of the NMOS device overall increased by almost 50 per cent compared with the IBM work presented at the VLSI Technology Symposium last year.

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