Altera moves to 55nm for non-volatile programmable logic

Altera has moved to a 55nm embedded flash process to continue its Max series of non-volatile FPGAs.

Although the successor to Altera’s long line of Max complex programmable logic devices (CPLDs), the Max 10 devices have much more in common with the company’s Cyclone and Stratix FPGAs, using more or less the same logic elements, digital signal processor (DSP) blocks and embedded SRAM cores.

“This product bridges the CPLD world into the FPGA world because it brings a lot of system level functions. We are finding that those markets are merging,” said Shelly Davis, director of strategic marketing for broad-based products at Altera.

As with the last couple of generations of Max devices, the programmable elements are SRAM-based but configured in on-chip flash in a process that takes up to 10ms on the largest 50,000 logic-element device.

To allow live updating of the configuration or hold a backup design, there are two sections of flash that are activated based on the state of a bit in a control register. For designs that are not likely to be updated in the field, Altera has provided the option to use the second flash array as regular memory alongside another section devoted to storing persistent data and security keys, which can be decrypted using a onchip 128bit AES unit.

The Max 10 devices contain two 12bit successive-approximation analog-to-digital converters (ADCs), fed by up to 18 input channels. A key target application lies in multi-camera vision systems. “I feel that machine vision is going to be an up and coming market,” said Davis, adding that these applications call for input from a number of image sensors. Another target, coupled with the DSP blocks, is motor control.