First fabless, now labless

By Michel Villemain |  No Comments  |  Posted: June 1, 2010
Topics/Categories: EDA - DFM  |  Tags: , ,

Product engineering services can be efficiently outsourced and even the biggest players are doing it, says Michel Villemain

As IC technology scales down to 40nm and below, only a handful of major semiconductor manufacturers and foundries will be able to sustain the required investments in equipment and expertise to produce next-generation devices themselves. Elsewhere, the supply chain demands a combination of partnership and outsourcing. Here we discuss a new ‘labless’ business model that enables chip companies to outsource product engineering so they can maintain their focus on design and production.

IDMs and fabless companies are already outsourcing many critical test and analysis functions as they prepare to go to market with new devices. This trend is set to accelerate as increasingly complex and specialized techniques and tools are needed to produce each new generation’s products, and this leads in turn to the chronic underutilization of expensive, existing tools. For example, the growing adoption of 3D semiconductor technologies is already fueling this change as it demands new skills, reliable processes and specialist equipment for product engineering (e.g., characterization and failure analysis/debug).

Our company, Presto Engineering, recently announced a three-year agreement to collaborate on developing test, reliability and failure analysis solutions for 3D devices with CEA-Leti, the French research agency. The program will focus on characterizing through-silicon via (TSV) reliability, defect susceptibility and electrical performance, identifying existing test protocols that are appropriate for 3D structures and bringing up new diagnostic methods and tools to identify root cause of failures.

This collaboration is a logical and strategic evolution of the ‘labless’ business model, which enables chip companies to outsource critical test and failure analysis functions that require high levels of capital investment and dedicated personnel.

The model is based on providing critical services covering state-of-the-art ATE for digital and RF, reliability testing, failure analysis and fault isolation. In effect, Presto acts as an outsourced product-engineering department for fabless companies and IDMs, to help relieve the intense schedule pressures that product engineers (PE) face.

The evolution of the PE’s role 

The PE brings a newly designed device from tape-out (design completion) to volume manufacturing, and his role usually continues up to the end of product life (Figure 1). The PE’s contribution to the business is to minimize time-to-volume (T) and time-to-profit by driving a sharp ramp to maximum yield (α).

Figure 1
Product engineering in semiconductor product life

In the past, manufacturing would develop a process independently of the designs being planned for it. Its focus was on contamination, process modules (e.g., lithography, film, etch) and process control. With the emergence of foundries and then what TSMC now terms ‘mega-fabs’, manufacturing became remote and was handled as a function (by a supplier). Most of the emphasis was on the chip design team.

As the system-on-chip (SoC) concept came of age, the ability to integrate various elements (e.g., control, memory, RF and analog) made the difference between products and between companies. Designers bring significant value to this work. 

High stakes 

Shrinking market windows

The stakes changed with newer process technology. With finer lithography, millions of gates can be integrated, leading to larger, much more complex designs. The initial investment that has to be made in a new high-end design can exceed $25M, and that is not even for one using leading-edge technologies. Any delay in the release of a new product hits revenues hard, severely impacting first-to-market advantages. Additionally, market windows are shrinking. PEs are now at the center of a very high-stakes game. 

Assessing failures

The program responsibility for such re-spin decisions falls on both the product engineering staff and the product-line marketing team. PEs must assess the criticality of failures, the availability of work-arounds, the risks associated with re-spin, and the opportune time for the work. 

This puts incredible pressure on the PE, as time-to-volume and time-to-money is the leading indicator that makes or breaks a new design program—and sometimes the entire company. 

New challenges

PEs face increasingly tough challenges when it comes to accelerating their product ramp in manufacturing. As described above, the ‘drive to ramp’ is dictated by growing upfront costs and by the increasing risk as ramp-time lengthens.

With investment going up, PEs must deliver a device yielding well and fast. Any week lost, any yield point missed, reduces the return on a huge investment. Most important, a delay in volume shipping puts the company at risk of missing a shrinking market window and/or leaving it open to competition. 

Designs are more remote 

There was a time when a design could be understood in depth by several individuals. The way to test a given design would be easily conveyed through a series of meetings between them. When a device failed at ATE, the test engineer (or PE) would come back to one of the designers for either an explanation of what failed, or for a new set of test patterns to localize the failure(s). With today’s designs packing millions of gates, this approach is no longer practical.

Designs are produced by a multitude of automated software tools that take a logical-level input and automatically generate databases containing a physical implementation (i.e., place & route, layout) along with a test solution. Test patterns are generated by automated test pattern generation (ATPG) tools. The most critical designs are tested through scan-based elements, and built-in self-test ensures that internal structures are tested. 

As a consequence, PEs have lost visibility, not only of the design itself, but also into the link between the test solution and the logical design. Naturally, today’s more automated methodologies have been designed to streamline the whole flow and help produce the best test solutions possible at the least cost possible. And most of the time, they work. But when they do not, PEs have to rely on their mastery of complex tools as opposed to the information they can gather from a few individuals.

Process is more remote 

With new process technologies, design implementation has become more of an art than a science. To reduce the marginal cost of lithography, steppers have been stretched across several process generations. This, however, made the implementation of a design more remote and mysterious, since what is actually printed on silicon is now less and less what was initially instructed in the layout. 

As design size and complexity have required that PEs communicate directly with the designer, RET demands that they have direct contact with process and yield engineers. What is implemented by the process engineering staff is not what PEs have given them at tape-out; it has been significantly transformed by RET. While PEs are expected to resolve issues very quickly, they are more and more isolated from the natural source of solutions.

The toolbox is exploding

Today’s engineers have a plethora of tools with which to address the various challenges.

On the design side, design-for-test (DFT) methodologies have grown toward the adoption of scan-based design. DFT is quite successfully embodied in an effective framework from design to test. It usually supports the automatic generation of the test 

solution with reasonable coverage, and also provides methods for mapping test failures back to the design.

This has eased the burden PEs must carry at the test level. Since they typically have ATE/test backgrounds, the community has widely adopted these strategies (as have ATE manufacturers). However, PEs today must juggle multiple software platforms and more comprehensive test frameworks.

At the same time, failures now tend to have physical or material components in addition to more traditional electrical ones. Techniques and tools have been developed to address this wider range of issues, but while they may ‘complement’ electrical test techniques, they still use dramatically different technologies. 

Back in the 1990s, PEs could depend on simple emission techniques (liquid crystal) with simple cross sections and SEM images to get the job done. Now they must work with different levels of emission, laser-based techniques and silicon frontside & backside, as well as more complex mechanical and (more importantly) electrical set-ups.

For example, previous localization techniques used to require that a device be powered up. New localization techniques require that the device be exercised at speed, or even that it is controlled as under ATE, so the device execution can be stopped on specific test steps/vectors.

New solutions needed 

We do not just need PEs anymore; we need more packaged product engineering solutions.

The industry has invested in tools that can cope with today’s level of complexity, but it has fallen short when it comes to providing a framework that makes so large a tool set usable.

PEs should be able to focus on where they bring the most value to making projects successful—the organization and execution of the transfer of new designs into volume manufacturing, and especially how they facilitate and accelerate each step in that process. It is counterproductive to have them invest time, energy and expertise in solving highly specific issues. 

While DFT provides a framework for taping-out new designs, by streamlining the path from logical designs to designs, design for manufacturing (DFM) has evolved, incorporating restrictive design rules (RDRs) to attempt to deal with process complexity. Most advanced designs can be efficiently tested, but they still come back from the fab with issues, some almost intractable.

Help for PEs

In this situation, PEs need all the capabilities and tools that will allow them to address such issues and push designs forward. Such capabilities include test and analytical means of exercising, observing and measuring devices, usually in combination. This requires ATE knowledge, along with fault isolation methodologies using emission and laser-based techniques. It also requires knowledge of new analysis technologies (SEM, STEM, TEM, FIB, Dual Beam, AFM, etc.) and ready access to service providers with the expertise to use them efficiently in combination with the previous tools. 

Supporting PEs in their critical task—allowing them to remain focused on pushing their new design through volume manufacturing—while helping them solve the key issues that new technologies bring with them, requires a new business model: a labless model that allows PEs to outsource the test and analysis required by new devices in today’s semiconductor environment.

Michel Villemain is CEO of Presto Engineering (, a product engineering services company operating from its hubs in Silicon Valley, Grenoble and Normandy.

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