Fully grounded

By Paul Dempsey |  No Comments  |  Posted: June 1, 2010
Topics/Categories: EDA - IC Implementation  |  Tags:

Disneyland might be next door, but DAC 2010 is stressing a real-world perspective on chip design. We spoke to general chair Sachin Sapatnekar.

The 47th Design Automation Conference takes place at the Anaheim Convention Center, June 13-18, and according to its 2010 general chair, Sachin Sapatnekar, a major trend through the event will be outreach.

“We looked at our constituencies. There are the people who publish research papers, people like me, and we would come anyway. Then there are the people who exhibit. And within reason they continue to come—we have to listen to their needs and make DAC attractive to them, but these are people who’ve also been coming for years,” he says. “But while you can’t minimize the importance of either of those groups, we’re really looking to serve new audiences.

In one respect, Sapatnekar says he is here looking at the kind of engineer who more typically attends the International Solid State Circuits Conference. That echoes a criticism sometimes leveled at DAC: that while the exhibition looks to engage tool users, the technical conference is more focused on tool developers.

“And there is an issue there, particularly right now because of the economy,” he says. “If an engineer wants to come to DAC, he needs to come away with good user information, and you want to provide ways of doing that through the conference as well as the exhibition. If a guy can go to his boss and say, ‘Yes, I’m going to be looking at tools but I’m also going to be learning something,’ there’s a much better chance that his boss is going to say, ‘OK, go.’”

To that end, DAC launched the User Track last year, a series of presentations dominated by, as the name suggests, users talking about their real-world experiences with EDA software.

“Thinking of that ISSCC guy again, he also goes to a lot of the user group meetings, but the thing with those is that they are user-agnostic—they are dominated by a particular vendor’s software,” says Sapatnekar. “I don’t characterize our User Track as exactly user-gnostic, but we do think of it more in terms of what really happens, of engineers bolting together a number of tools from a number of sources to get the results they need. Mix and match to do the job.”

After last year’s “very successful experiment,” the User Track has been expanded and it is not the only recent initiative that is being scaled up for DAC 2010.

“One of the other things we’ve recently tried to do is collocate a lot more events alongside DAC. You saw that in San Francisco [last year], and we’ve extended the idea again,” says Sapatnekar. “It’s also a lot about what an engineer says to his boss to justify coming, because we know that budgets are under a lot of pressure. The boss might say, ‘Well, there are just the four sessions at the conference.’ But if there’s also a daylong meeting or workshop happening alongside that, it might swing the decision. More importantly though, it’s more potential information for the engineer.”

As a result, there are about 20 different events taking place next to the main DAC conference (see box), and a deliberately broad policy has been adopted in choosing and/or wooing them.

“We wanted to represent both the here-and-now and the relatively long term as well as all points in-between, and we also wanted to cover a wide range of topics,” says Sapatnekar. “So, if you’re looking at the very contemporary, we have, for example, two workshops on DFM [design for manufacturing] and yield issues and another on PDKs [process design kits].

“By contrast, and looking much further out, we then have a workshop on bio-design automation. Is that happening now? No, but it is being talked about now; it’s an area where things are starting to happen. And it also shows how broad we want the appeal of this concept to be.”

This breadth is also particularly apparent in the 2010 choice of keynote speakers. The first of these will be George Grose, CEO of GlobalFoundries (Tuesday, June 15).

“Obviously, they are a happening company in the industry right now,” says Sapatnekar. “But it’s also important to recognize generally the role that foundries play. We see it at DAC with them having a greater role themselves on the exhibit floor, in the partner booths and in the Pavilion—and, of course, there are the various flows offered by the foundry companies.”

Grose’s speech, “From contract to collaboration: delivering a new approach to foundry,” reflects that convergence, according to the executive’s own preview: “Chip design companies need to redefine relationships with their manufacturing partners, and foundries must create a new model that brings manufacturing and design into an integrated and collaborative process.”

The second keynote will be from Bernie Meyerson, fellow and vice president for Innovation at IBM, in a talk entitled “Echoes of DACs past: from prediction to realization, and Watts next?” The speech (Wednesday, June 16) will review many of the design challenges facing engineers in the post-Moore’s Law era (a topic on which Meyerson has spoken several times before, including at DAC), but also look forward to the impact of cloud computing.

“It’s unusual to invite someone back to DAC as a keynoter this early, but Bernie Meyerson is an exceptional speaker and we also felt that his growing role as an evangelist for the possibilities of cloud computing makes this address very timely,” says Sapatnekar.

“If you were to ask an engineer what ‘The Cloud’ is, obviously he’ll know, but I think there are a lot of questions about what it is going to mean for engineers. What is it going to mean for the products they design at one level, and what is it going to mean for how they use tools and how they are licensed at another? If we can start to address those types of questions through DAC then we’re doing our job.”

The third keynote then feeds directly into one of the other aggressive trends in chip design today.

“We’ve made Thursday [June 17] an embedded/system-on-chip (SoC) enablement day—and it’s largely about trying to help with this seamless transition toward a more integrated world of hardware and software design,” says Sapatnekar. “There has been pressure for the conferences on both sides of that to reflect more of what is happening. Last year, DAC had a virtual platforms strand and, like the User Track, it was very successful, so we’ve expanded things this year. And we’ve also extended this into the third keynote.”

That speech will be given by Iqbal Arshad, corporate vice president of Innovation Products at Motorola Mobile Devices. “He’s the guy who really drove development of the Droid [handset] at Motorola, so he’s got direct, immediate experience of the real challenges here. Bringing in someone like that to keynote and then having engineers from the Atom side of Intel, from ARM and elsewhere look at this whole embedded and SoC challenge means that people should get some really good take-aways.”

It’s worth remembering that the popular elements of the traditional DAC program are all present and correct. There is the usual plethora of technical sessions and, in the exhibit hall, a full set of Pavilion panels open to all attendees, starting with analyst Gary Smith’s invaluable overview of the state-of-play in EDA.

For his part, Sapatnekar is looking to a program that will live up to two benchmarks. “If enough people can come to DAC and learn something, genuinely feel that the trip was worth it—that’s my definition of success. And it’s probably true that you have to spread the net very wide these days to make sure you do that,” he says. “The second thing, of course, is that you don’t want to go into the red.”

The DAC website is now online at www.dac.com

Collocated with DAC 2010

The following events will also take place during this year’s Design Automation Conference. All events take place in the specified room at the Anaheim Convention Center unless another venue is cited.

IEEE International High Level Design Validation and Test Workshop (HLDVT 2010)
Friday, June 11, 2010 – Saturday, June 12, 2010 — Room 304A

International Symposium on Hardware-Oriented Security and Trust (HOST)
Sunday, June 13, 2010 – Monday, June 14, 2010 — Room 205AB

8th IEEE Symposium on Application Specific Processors (SASP 2010)
Sunday, June 13, 2010 – Monday, June 14, 2010 — Room 207D

DAC Workshop on Synergies between Design Automation & Smart Grid
Sunday, June 13, 2010, 8:00am-6:00pm — Room 206A

Multiprocessor System-On-Chip (MPSOC): Programmability, Run-Time Support and Hardware Platforms for High Performance Applications at DAC
Sunday, June 13, 2010, 8:00am-5:00pm — Room 209AB

IEEE/ACM 12th International Workshop on System Level
Interconnect Prediction (SLIP)
Sunday, June 13, 2010, 8:15am-6:30pm — Room 207AB

DAC Workshop on Diagnostic Services in Network-On-Chips (DSNOC) – 4th Edition
Sunday, June 13, 2010, 8:30am-5:30pm — Room 210AB

System and SOC Debug Integration and Applications
Sunday, June 13, 2010, 9:00am-6:00pm — Room 208AB

Design for Manufacturability Coalition Workshop – “A New Era for DFM”
Sunday, June 13, 2010, 1:00pm-4:00pm — Room 207C

North American SystemC Users Group (NASCUG 13 MEETING)
Sunday, June 13, 2010, 3:30pm-7:30pm — Hilton Anaheim

IWBDA: International Workshop on Bio-Design Automation at DAC
Monday, June 14, 2010 – Tuesday, June 15, 2010 — Room 303CD

4th IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y)
Monday, June 14, 2010, 8:30am-5:30pm — Room 207AB

DAC Workshop on “Mobile and Cloud Computing”
Monday, June 14, 2010, 8:30am-5:15pm — Room 206A

Choosing Advanced Verification Methods: So Many Possibilities, So Little Time
Monday, June 14, 2010, 9:00am-5:00pm — Room 208AB

DAC Workshop: More Than Core Competence…What it Takes for Your Career to Survive, and Thrive! Hosted by Women in Electronic Design (WWED)
Monday, June 14, 2010, 11:30am-2:00pm — Room 204C

Advances in Process Design Kits Workshop
Monday, June 14, 2010, 1:00pm-4:00pm — Room 207C

NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2010)
Tuesday, June 15, 2010 – Friday, June 18, 2010 — Room 205AB

ACM Student Research Competition
Tuesday, June 15, 2010 – Wednesday, June 16, 2010 — Room 204AB

IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’10)
Thursday, June 17, 2010 – Friday, June 18, 2010 — Room 204C

19th International Workshop on Logic & Synthesis (IWLS)
Friday, June 18, 2010 – Sunday, June 20, 2010 — University of California, Irvine

Comments are closed.


Synopsys Cadence Design Systems Siemens EDA
View All Sponsors