In his early days in the semiconductor industry, Morris Chang Morris Chang was one of the “non-Texans” to Texas Instruments and was a manager struggling with the question of how to get individual transistor yields to somewhere around three or even four per cent. One of his colleagues – another immigrant to the Lone Star […]
This year’s general chair of Design Automation and Test in Europe is Donatella Sciuto, a full professor at the Politecnico d iMilano in Milan, Italy. She received her Laurea in Electronic Engineering from the Politecnico di Milano in 1984 and her PhD in Electrical and Computer Engineering in 1988 from the University of Colorado, Boulder. […]
The semiconductor industry faces increasing challenges in the design of complex systems-on-chip, and while some have sprung from new, only recently anticipated sources, others are, in fact, very familiar. Foremost among these are the interconnect delays caused by the increasing influence of parasitic networks. Parasitic inductance is also a growing concern. The causes of parasitic […]
SystemVerilog, the standard that originated from Accellera and is now IEEE1800, is not just for Verilog users. VHDL users can also improve their design processes using its proven verification features. Anyone involved in systemon- chip (SoC) design may face a mixed-language environment and will appreciate being able to leverage SystemVerilog with the VHDL portions of […]
Changes in defect distribution, increasing design complexity and pressures from the specialist I/O and packaging arenas are creating a dilemma during component test. On the one hand, the generation of more test patterns would appear to be necessary; but on the other, fewer test ports are available. The article describes a strategy for addressing this […]
Electronic system level (ESL) design is moving to a new stage in its development, advancing from a proof-of-concept environment to one that is seeing its adoption and deployment at the forefront of design. The article terms this shift ‘ESL 2.0’. The reason for this goes beyond mere marketing hype. Inherent in the transition defined above […]
Cswitch’s CS90 Configurable Switch Array device has an interconnect structure, the dataCrossconnect network, that delivers bandwidth at 40- 100Gbps for packet-based applications. For packet handling tasks, the chip includes embedded configurable blocks, Configurable Packet Engines, that support functions such as frame parsing, CRC and hashing, and fast address look-ups, all at up to 1GHz. For […]
How visibility-enhanced debug works The emergence of ‘visibility enhancement’ technology provides verification teams with an optimal trade-off between simulation performance and signal visibility. Visibility enhancement enables a methodology consisting of an analysis-driven partial signal dumping procedure that limits the impact on emulation performance while still providing full signal visibility for debug. These are some key […]
Today’s increasingly complex designs typically need to undergo verification at three different levels: block, interconnect and system. There are now well-established strategies for addressing the first two, but the system level, while in many ways the ultimate test, remains the weakest link in the verification process. System verification normally begins only after a prototype board […]
Long before the first portable computer batteries exploded, and even before anyone had the first visions of building massive data centers in the cold northwestern states of Oregon,Washington and Alaska, power consumption by electronic devices was a tough problem for chip designers. The difference now is that we are trying to manage power in ever-smaller […]