Volumes

September 1, 2008

Modeling embedded systems using SystemC extensions

SystemC AMS extensions introduce new language constructs for the design of embedded analog/mixed-signal systems. This paper presents the novel modeling language for analog and mixed-signal functions that supports design and modeling of telecommunications, automotive and imaging sensor applications at various levels of abstraction. A simple example illustrates how new features facilitate a design refinement methodology […]

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September 1, 2008

Clock domain crossing: guidelines for design and verification success

Clock domain crossing (CDC) errors can cause serious design failures. These can be avoided by following a few critical guidelines and using well-established verification techniques. The guidelines include: When passing 1bit between clock domains: register the signal in the sending clock domain to remove combinational settling; and synchronize the signal into the receiving clock domain. […]

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September 1, 2008

The state we’re in

UK-based analyst group Future Horizons has been organizing its international electronics forums for 17 years and they continue to provide an invaluable look into what the industry’s top tier of managers is thinking. It is one thing to get your own wise analysts to pronounce on tomorrow’s market, but it is something else entirely to […]

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September 1, 2008

An industry-as-laboratory approach to dependability for high-tech systems

The dependability of high-volume embedded systems, such as consumer electronics devices, is threatened by a combination of rapidly increasing complexity, decreasing time-to-market, and strong cost constraints. This environment poses challenging research questions that are being investigated in the Trader Project, following an industryas- laboratory approach. This paper describes the vision behind the project and reviews […]

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June 1, 2008

VHDL moves toward 4.0

Version 4.0 of the VHSIC Hardware Design Language was approved by Accellera and passed to the IEEE to begin its formal standards balloting process earlier this year. The article previews some of the key additions and extensions that form part of VHDL in the following areas: Property Specification Language Intellectual Property Protection Hierarchical names Extensions […]

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June 1, 2008

Systems design automation for real

The Design Automation and Test in Europe (DATE) conference is a comparatively young event—it reached only its 11th edition this March. Nevertheless, it has now firmly established itself on the EDA calendar and this year significantly extended its scope to become the world’s most important electronic systems design automation conference. At the same time, it […]

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June 1, 2008

STIX to the task

Before 2001’s historic downturn, the semiconductor industry was primarily driven by the corporate and enterprise markets. This bias led to a somewhat predictable three-year business cycle of peaks and troughs. Corporate buying practices, technology requirements and IT replacement policies are all relatively easy to predict—right down to the nature of the semiconductors that underpin the […]

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June 1, 2008

Start Here

With this fourth anniversary issue of the EDA Tech Forum Journal, we have begun to make a few changes—more will follow over the coming months. In terms of content, the most obvious change is that we have introduced a new section dedicated to the role of embedded technologies in the design fl ow. It is […]

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June 1, 2008

Sensium: A 1V micropower SoC for vital-sign monitoring

This paper describes the main design components and methodology priorities for development of the Sensium system-on-chip for wireless body sensor networks. The device is targeted at vital-sign monitoring and related medical applications. The SoC integrates an ultra-low-power wireless ISM band transceiver, hardware MAC, microprocessor, I/O peripherals, memories, 10b delta-sigma, analog-to-digital converter and custom interfaces. The […]

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June 1, 2008

Multi-corner multi-mode signal integrity optimization

Signal integrity (SI) is an ever-growing problem as more interconnect effects and fast clocks increase the chances of crosstalk noise and glitches as well as unexpected signal delays. There has been a significant increase in SI-related timing violations due to the increasing influence of lateral wire capacitance in designs at 65 and 45nm. A fast-increasing […]

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