Visibility enhancement eases system validation for multicore SoCs

By Mike Dickman |  No Comments  |  Posted: December 1, 2007
Topics/Categories: EDA - Verification  |  Tags:

How visibility-enhanced debug works

The emergence of ‘visibility enhancement’ technology provides verification teams with an optimal trade-off between simulation performance and signal visibility. Visibility enhancement enables a methodology consisting of an analysis-driven partial signal dumping procedure that limits the impact on emulation performance while still providing full signal visibility for debug. These are some key components:

  • Visibility analysis analyzes RTL and netlist representations to determine the minimum set of essential signals required for full visibility. This provides the flexibility needed to target an entire design or only those blocks and signals of interest.
  • Data expansion automatically computes missing signal data that is based on essential signal data and design knowledge provided by the RTL or the netlist. The data regeneration process is optimized by computing ‘on-demand’ only those values required for debug.
  • Abstraction correlation automatically maps gate-level verification results to RTL design descriptions. This interoperates seamlessly with the data expansion engine to enable analysis and debug with full visibility into the RTL design

P.A. Semi’s PWRficient family of 64bit multicore processors is an example of the next-generation systems-on-chip (SoCs) that are redefining the cost, power and throughput efficiency of high-performance processing for embedded data communications as well as applications in the consumer, portable, network, server blade, and telecommunications spaces. In order to achieve optimized performance per-watt for a recent design, the P.A. Semi verification team had to overcome especially daunting signal visibility challenges during late-stage verification and system validation.

The chip

The first PWRficient platform processor is a dual-core chip running at 2GHz with typical power dissipation in the range of 5-13W, depending on the application. The 20-million gate ASIC and custom design (excluding memory) is comprised of mostly internally designed intellectual property for CPU,memory and I/O interfaces. The PA6T-1682Mimplementation features two DDR2 memory controllers and 2MB of L2 cache. A flexible I/O subsystem supports eight PCI Express controllers, two 10GbE XAUI controllers and four GbE SGMII controllers sharing 24 SERDES lanes.

Based on the Power architecture from IBM, the processor design integrates northbridge, southbridge and network-interface functionality into a single chip. Dubbed a platform processor, it integrates what is typically a three- to five-chip platform into a single device. This high level of on-chip integration dramatically reduces the cost of silicon while delivering high throughput and low latency. However, it also makes the process of understanding the internal behavior of the design exponentially more difficult.

Visibility enhancement

P.A. Semi’s verification strategy revolves around the use of hardware emulation early in the design phase. This allows the rapid execution of diagnostic tests and enables the prompt running of real-world operating systems and applications. In this environment, it can take hours and hours to get to the point of failure, and this is before the debug process can even begin. For the PWRficient project, the team needed a means of gaining sufficient visibility into the design that would not place too great a burden upon performance or design and verification resources.

To address this ‘observability’ problem head on, P.A. Semi adopted an industry-standard top-down design flow that employed a mix of EDA tools. It included Novas Software’s Siloti Visibility Enhancement (VE) products as well as the ZeBu hardware-assisted verification platform from EVE Design Automation.

The verification team focused on two specific goals:

  1. They wanted to debug on the emulation platform prior to first silicon.
  2. Then, once silicon was ready, they wanted the ability to extract necessary signal data and debug in the context of the register transfer level (RTL) description to better understand design behavior.

Debug on the emulation platform

Emulation systems can present significant visibility challenges because of the expense of observing internal signal data and the unfamiliar gate-level representation of the design. Because these verification systems are hardware-based, engineering teams must run multiple iterations of synthesis and compilation steps to configure or insert debug logic, and then re-execute the tests.


Figure 1. How Siloti works for emulation

The Eve emulation environment is constructed around Xilinx FPGAs. Using the FPGAs’ built-in scan, it is possible to dump the state elements in the design at no extra hardware cost. In addition to capturing the design’s state elements, it is possible to insert visibility probes on combinational logic in the design at the cost of FPGA resources. However, setting up these probes is both expensive and time consuming. As well as the problem of limited visibility, there is also the fact that it can be difficult to correlate emulator dumps based on gatelevel net names with the non-synthesized RTL logic waveforms. By using the Novas Siloti VE products, P.A. Semi was able to achieve full visibility into the design still at no additional hardware cost, and automatically map synthesized gate netlist names into RTL signal names for easy debug.

The initial bring-up of the P.A. Semi emulation environment involved executing small test cases on the EVE platform and comparing the results against a simulation model. When mismatches occurred, dumps were collected from both environments and compared.

Since emulation produces a gate-level state element dump and simulation produces a complete RTL signal dump, isolating problems in the models could be very difficult.

The debug process involved finding differences in common state element data in both dumps.When a difference was found, all of the state elements feeding the problem logic cone were examined for differences. Tracing continued backward until the initial failure was determined. It could take a full day to isolate a single problem in the model because of the number of logic levels that needed to be traced, the complexity of the logic cones involved, and the nature of the gate-to-RTL name mapping.

Implementing an optimized approach

For the development of the PWRficient family, the P.A. Semi team instead deployed an optimized verification methodology that combined VE technologies with emulation.

The process involved taking the essential gate-level signal data from emulation, mapping the gate-level names to RTL, and inflating the data to produce a complete full-visibility RTL signal dump. The resulting emulation and simulation dumps could then be directly compared.

The combination of data expansion and abstraction correlation technologies, working transparently on a limited amount of signal data, enables debug automation to trace problems on the RTL source code.

In the case of emulation systems such as ZeBu, abstraction correlation processes the gate-level signal data dumped from the registers to their RTL counterpart. The mapped data is then processed with data expansion to make RTL combinational values visible. The combined impact of these two technologies is RTL-centric debug with a high visibility of most internal signals in the emulated design.

Using this improved debug methodology, a difficult problem could be debugged in an hour or two instead of in a full day. In one case in particular, the P.A. Semi team came across a circuit that failed in emulation, but passed in simulation.When the two dumps were compared, emulation did not match up with simulation. Using its traditional approach to debug, they would have been forced to manually examine the state elements and trace back through logic to find the source of the problem, a very time-consuming process.

Instead, limited signal data from the emulation dump was processed, missing signal data was automatically regenerated, and all of the information was then correlated to RTL. Examining the RTL, the team quickly identified the problem to be a circuit that incorrectly used a synthesis one-hot directive.

Debug of large programs

Visibility enhancement continues to be a cornerstone of the system validation process established by the P.A. Semi verification team. It has played and continues to play a leading role in the verification of all versions of the PWRficient family of processors. To this end, P.A. Semi also applied VE techniques to debug operating system and application failures in emulation and on silicon.Various methods were used to create a trigger to start the data capture prior to a failure. Following the trigger point, an essential state element dump was generated that included the failure. This data was then mapped to RTL signal names and inflated using the Siloti VE technology. Depending upon the failure, the problem could then be debugged by comparing the results against an instruction set simulator and/or by careful examination of the waveform and RTL.

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P.A. Semi was acquired by Apple in 2008

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