USB Type-C: easier for users, harder for designers

By Gervais Fong |  No Comments  |  Posted: August 26, 2015
Topics/Categories: IP - Selection  |  Tags: , , , ,  | Organizations:

Gervais Fong is a senior product manager for mixed-signal PHY IP at Synopsys.Gervais Fong is a senior product manager for mixed-signal PHY IP at Synopsys. Gervais has over 15 years of experience holding product marketing and product management positions covering ASIC, FPGA, EDA, and IP products.

The introduction of the reversible USB Type-C connector promises to ease users’ frustration with plugging in USB devices – whichever way the plug is inserted, the connection should just work.

USB Type-C also includes support for USB 3.1 at data rates of up to 10Gbit/s, power delivery up to 100W, audio multiplexing, and alternate modes that handle video signals such as DisplayPort and MHL.

It’s no wonder that hundreds of vendors are rolling out products that support USB Type-C. In fact, more than one hundred vendors of everything from cables to laptops attended the first USB Type-C plugfest in July 2015 to test their products’ and prototypes’ interoperability.

Although the industry has been working with USB for decades now, implementing a Type-C connection brings new challenges. For example, when running at 10Gbit/s, the voltage swing on the data lines is less than 0.5V. Designers need to implement equalizers in the PHY at the receiving end of a connection to take the incoming signal, whose eye will essentially be closed, and apply the equalization necessary to open the eye and reveal whether the signal represents a logic 0 or 1.

There are a number of other challenges in implementing a Type-C connection, especially at the full 10Gbit/s data rate of the USB 3.1 specification.

Rethinking the PHY

For example, the reversibility of the connector demands re-architected PHYs in the implementation. When running at USB 2.0 data rates, designers can indicate which way the connector is plugged in by using a couple of resistors to short two data paths going into the PHY. The PHY has enough performance margin at the lower USB 2.0 data rates to handle the reflections that the short causes.

For USB 3.0 and 3.1 data rates, designers need to implement two data paths to handle the higher rates. With the connector in one orientation, the system connects to one data path, while in the other orientation, it connects to the other. Dual data paths are necessary because at 5 and 10Gbit/s, shorting data paths to indicate orientation would cause too much signal reflection to resolve the data.

Designers need to decide how to address this issue. One solution is to use two PHYs, one for each orientation. The downside of a dual-PHY solution is the 20 to 25% area penalty to implement two SuperSpeed and two Hi-Speed data paths, as well as needing two PLLs and two sets of power, ground and data pins. The end result is a system having one more Hi-Speed data path than it really needs.

A more efficient implementation would use a PHY that has been optimized for the USB Type-C specification with two SuperSpeed data paths, one Hi-Speed data path, one PLL, and one set of power, ground and data pins.

Which implementation designers choose depends on their end application. Highly cost-sensitive markets will choose the area and silicon savings realized by avoiding an extra Hi-Speed datapath, as well as reducing the pin count by up to 40%.

USB Type-C signalling

A second challenge of implementing USB Type-C is the signal complexity required across the 24-pin connector. The USB Type-C spec defines configuration channel (CC) and power delivery (PD) signals to define parameters such as the orientation of the connector, how much power can flow over any cable that is plugged into a Type-C port, and when the connector is used in an alternate mode for video or audio.

Supporting both the CC and PD signals requires additional logic: the PD messaging controller and the CC logic. Part of the design challenge is dealing with the two signals, which can happen at different voltages, depending on the combination of signals that are active at the time.

The Type-C spec has also done away with the concept of USB On-The-Go, a way of signaling whether a port is being used as a host or a device, and instead replaced it with the concept of a Dual Role Port. The On-The-Go protocol used the ID pin to signal whether the port was acting as a host or a device, but with Type-C this signal is absent and so the work is done using a PD messaging signal – further complicating the PD signal implementation.

Systemic issues

The Type-C connector promises to make USB users’ lives easier, but at the cost of making designers lives a bit more complicated. Designers will have to decide whether they want to support USB 2.0, 3.0 and/or 3.1, how to handle power delivery, and whether to support alternate audio and video modes.

The implementation of USB Type-C will also have systemic implications. For example, if the SoC is going to support power-delivery capabilities, designers may choose to use an external power-management IC that meets all the relevant safety qualifications. This would mean partitioning the PD and CC logic implementation, perhaps between the PHY and a separate PMIC, the main system CPU, or even a dedicated external microcontroller.

Synopsys’ comprehensive set of USB controller and PHY IP has been selected in more than 3,000 USB design wins and proven in almost three billion units shipped. It’s that deep, direct design experience that enabled us to develop USB 3.1 PHY IP optimized for use with the Type-C connector, as well as the supporting tools and verification environment necessary to implement Type-C functionality—making life a little easier for designers.

More info

DesignWare USB-C PHY IP

Webinar: Designing SoCs for USB Type-C Products

Article: Converting Existing USB Designs to Support USB Type-C Connections

Article: Implementing USB Type-C in High-Speed USB Products 


Tech Design Forum’s seven-article series on USB 3.0 starts here

If you are new to designing with USB, or looking for tips on implementing USB 3.0 IP, attend Synopsys’ ‘USB 3.0 University.’ Topics in this instructional video series range from a basic USB overview, to implementing USB on FPGAs, to top-level synthesis, and more. Click on the links below.

Why USB 3.0?

USB 3.0 Overview

USB 3.0 Functional Layer

USB 3.0 Protocol Layer – Part 1

USB 3.0 Protocol Layer – Part 2

USB 3.0 Link Layer

USB 3.0 Physical Layer


Gervais Fong is a senior product manager for mixed-signal PHY IP at Synopsys. Gervais has over 15 years of experience holding product marketing and product management positions covering ASIC, FPGA, EDA, and IP products. Gervais holds a Bachelor of Science degree in Electrical Engineering and Computer Science from the University of California, Berkeley.

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