Verification

Carbon Design Systems' CTO Bill Neifert argues that his company's deal with Samsung sends a clear signal, whether or not you're one of his customers.

Shrinking process nodes, rising power efficiency goals and burgeoning device functionality are stretching existing DFR techniques to their limits. This scalable methodology looks to address the shortfall.

The verification challenge is best addressed by a combination of highly targeted tools, according to Pranav Ashar, CTO of Real Intent.

Assertions are already used in pre-silicon verification and can help halve debug time. So why not synthesize assertions into real logic gates in the final silicon, to catch those unexpected bugs that make validation so much harder? Here’s how.

MCMM analysis is a technique intended to provide high-confidence results for timing closure and other metrics without performing exhaustive simulation of all possible IC conditions.

The value of the emulation market has almost doubled in the last four years as the technique becomes increasingly valuable to hardware/software co-verification.

An overview of the Open Source VHDL Verification Methodology and two of the libraries it uses.

Can emulation save energy and space, as well as time, during the verification process? Some argue so.

Richard Pugh reflects on efforts to cut through the tangle of cables and make emulation easier.

This extract from the Synopsys and Xilinx-authored "FPGA-Based Prototyping Methodology Manual" outlines a number of valuable strategies supported by brief project case studies.