Verification

June 20, 2011

Inexact computing means knowing exactly what to cut

Pruning back circuits can boost performance for some applications.
Article  |  Tags: , , ,
June 2, 2011

Efficient RC power grid verification using node elimination

To ensure the robustness of an integrated circuit, its power distribution network (PDN) must be validated beforehand against any voltage drop on VDD nets. However, due to the increasing size of PDNs, it is becoming difficult to verify them in a reasonable amount of time. Lately, much work has been done to develop Model Order [...]
February 25, 2011

Firmware verification using SystemVerilog OVM

Your current verification strategy, no matter how robust, may not always satisfy the latest demands placed upon it given the rate of change in semiconductor design. To stay at the forefront of innovation, you must be willing and able to take advantage of the potential in emerging and evolving technologies. It is not simply that […]

Article  |  Tags: , ,
February 25, 2011

Planning reset strategies: flow and functionality in OVM verification components

The article describes a methodology and appropriate code for developing a reset strategy that will work within a verification process. Specifically, the proposal has been drafted within the terms of the Open Verification Methodology.
Article  |  Tags: ,
February 25, 2011

OVM testbench API for accelerating coverage closure

Constrained random testbenches excel at quickly hitting the majority of coverage but their effectiveness trails off as coverage closure nears completion. This paper describes a testbench API that sits on top of OVM sequences allowing the existing constrained random infrastructure to be guided, enabling faster, more efficient coverage closure. Design and verification engineers can use [...]
Article  |  Tags: , , ,
December 14, 2010

An introduction to System Verilog assertions

Assertions and assertion-based verification (ABV) are hot topics, but many engineering teams remain unfamiliar with the benefits they bring to the design and verification process. This article discusses the rationale behind them, the value they bring across the design and verification process, and offers a step-by-step approach to implementing them.
Article  |  Tags: ,
September 10, 2010

Symbolic simulation speeds timing closure

Timing closure is a key challenge for today’s complex system-on-chip designs. Static timing analysis (STA) tools automatically analyze signal paths in a design and identify timing-critical paths that limit the clock frequency that can be achieved. Paths that can never be functionally activated or that require multiple cycles for correct operation can be identified as [...]
Article  |  Tags: , ,
June 1, 2010

Device native debug and verification for FPGA

GateRocket's RocketDrive facilitates integration of an FPGA into an HDL simulator to provide a "native" execution of a design on its target FPGA device. The companion RocketVision tool provides software-debugging capabilities that directly identify and enable the rapid resolution of bugs. This article considers the use of these tools in a "device native" verification and [...]
Article  |  Tags: , ,
June 1, 2010

Application-specific library subsetting

The limited cell count of standard cell libraries is restricting the performance that designs can achieve without resorting to expensive and time-consuming techniques. This article describes the addition of extended cell libraries and novel synthesis tools to a traditional RTL-to-GDSII flow in a new methodology that helps to overcome this performance brake. The technique is [...]
Article  |  Tags: ,
December 1, 2009

Part 4- Power management in OCP-IP 3.0

According to Moore’s Law, system-on-chips (SoCs) should continually become more complex and integrate more components, enabled by each reduction in silicon technologies. However, power consumption does not follow the linear path implied here due to increasing leakage in deep sub-micron technologies. Hence, new power management techniques are needed to reduce power dissipation as much as […]

Article  |  Tags: , ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors