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MCMM
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![Sudhakar Jilla is group marketing director for place & route at Mentor Graphics.](https://www.techdesignforums.com/practice/files/2014/02/sudhakar-jilla.jpg)
Concurrency tackles MCMM issues head-on
![Carey Robertson is a director of product marketing at Mentor Graphics overseeing the marketing activities for layout versus schematic (LVS) and extraction products.](https://www.techdesignforums.com/practice/files/2013/12/Carey-Robertson-50.jpg)
FinFET parasitics come under control
20nm timing analysis – a practical and scalable approach
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Top-level MCMM closure for a multi-million-gate design
The art of low-power physical design
The architectures that underpin today’s traditional place-and-route tools are showing their age, largely because their static timing analysis engines cannot handle more than two mode/corner scenarios. Thus limited, the software struggles to effectively implement low-power design techniques beyond such established concepts as clock gating and multiple threshold voltages. Designers run into difficulties when trying to […]
Multi-corner multi-mode signal integrity optimization
Signal integrity (SI) is an ever-growing problem as more interconnect effects and fast clocks increase the chances of crosstalk noise and glitches as well as unexpected signal delays. There has been a significant increase in SI-related timing violations due to the increasing influence of lateral wire capacitance in designs at 65 and 45nm. A fast-increasing […]
Using multi-corner multi-mode techniques to meet the P&R challenges at 65 nm and below
Concurrent multi-corner, multi-mode analysis and optimization is becoming increasingly necessary for sub-65nm designs. Traditional P&R tools force the designers to pick one or two mode corner scenarios due to inherent architectural limitations. As an example of the problem, a cellphone chip typically needs to be designed for 20 mode/corners scenarios. In the absence of a […]
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