The increasingly onerous nature of physical verification at today’s nanometer process geometries requires the regular benchmarking of appropriate tools, if designs are to be realized in a cost-effective manner. However, the criteria for such benchmarking are all too often limited to relatively simplistic notions of ‘performance’. The article explains that the real cost of physical […]
Chip and package design are all too often still seen as separate stages in the design process. In today’s nanometer age and with the growing use of techniques such as system-in-package, this lack of integration can have catastrophic results. Package designers frequently encounter overly complex and un-routable silicon that requires multiple iterations to fix. Problems […]
The relative performance of a single processor has leveled off in the last decade. Built-in instruction-level parallelism is becoming less efficient because issuing more than four instructions in parallel has little effect on most applications. Meanwhile, recent attempts to boost performance have come dangerously close to the energy/power consumption ceiling. Dedicated hardware accelerators may prove […]
How important is it that the history of electronics is passed on from generation to generation of engineers in the ‘right’ way. OK, let’s acknowledge that, as in war, history is always dominated by the victors, not the losers. Let’s also admit that anyone with a career in this business wants its image to be […]
US factory-to-dealer sales of consumer electronics will surpass $155B in 2007, representing 7% growth, according to the most recent forecast from the Consumer Electronics Association. This performance will follow on from an expected $145B market in 2006, a year which surpassed even the most optimistic forecasts by logging growth of 13%. “The industry outlook is […]
There is a growing productivity gap in the design of embedded systems. One recent survey estimated that the number of lines of embedded code written per year is growing at a rate of 46% a year, although the number of developers available to write it is growing at only 7.5%. The problem is further compounded […]
Until recently, hierarchical design flows have been favored for the implementation of multi-million gate SOCs. However the rapid increases in design size brought on by nanometer process geometries have seen engineers seek to cope with the inherently block-based nature of such flows by seeking greater concurrency between the block implementation and chip assembly stages in […]
DATE 07 (April 16-20) marks an important milestone for the Design Automation and Test in Europe conference as it reaches its tenth edition. As we went to press, the main technical program was still being finalized, but DATE has again received record submissions, 933 against last year’s 834. The most obvious change in 2007 is […]
There has been a recent trend for tools originally aimed at ASIC designs to be applied to the design of high-volume projects aimed at markets such as consumer electronics. The article argues that there are a number of fundamental flaws in such a strategy. For example, an ASIC tool might be designed for an environment […]
We are now entering the tail end of an era, and many of us do not even know it. For as long as there have been microprocessors, there have been engineers and engineering teams whose job it was to create interconnects. Although this will undoubtedly continue in some companies, the increasing complexity of systems-on-a-chip (SoCs) […]
