Until recently, hierarchical design flows have been favored for the implementation of multi-million gate SOCs. However the rapid increases in design size brought on by nanometer process geometries have seen engineers seek to cope with the inherently block-based nature of such flows by seeking greater concurrency between the block implementation and chip assembly stages in […]
There has been a recent trend for tools originally aimed at ASIC designs to be applied to the design of high-volume projects aimed at markets such as consumer electronics. The article argues that there are a number of fundamental flaws in such a strategy. For example, an ASIC tool might be designed for an environment […]
We are now entering the tail end of an era, and many of us do not even know it. For as long as there have been microprocessors, there have been engineers and engineering teams whose job it was to create interconnects. Although this will undoubtedly continue in some companies, the increasing complexity of systems-on-a-chip (SoCs) […]
How do we bridge the gap between the highly abstract view provided by traditional system-level design and the detailed implementation in RTL? The article answers this question by describing the components within an ESL methodology and illustrating its use via customer case studies. The methodology uses the ARM RealView SoC Designer tool and Tenison Design […]
Look at what is supposed to be a stellar-performing market: displays. According to data from the Consumer Electronics Association, large screen plasma and LCDs are flying out of the stores.Yet the major suppliers spent much of Q4 2006 getting seriously beaten up on price. Moreover, the likelihood of a third technology entering that market, SED […]
A major issue faced by SoC design teams adopting 90nm and 65nm process nodes is the increase in yield fall-out. At 90nm it is estimated that 30% of yield fall-out is due to performance and signal integrity issues. As a result, accurate and cost effective at-speed manufacturing test and characterization has become evermore critical to […]
The increasingly onerous nature of physical verification at today’s nanometer process geometries requires the regular benchmarking of appropriate tools, if designs are to be realized in a cost-effective manner. However, the criteria for such benchmarking are all too often limited to relatively simplistic notions of ‘performance’. The article explains that the real cost of physical […]
Chip and package design are all too often still seen as separate stages in the design process. In today’s nanometer age and with the growing use of techniques such as system-in-package, this lack of integration can have catastrophic results. Package designers frequently encounter overly complex and un-routable silicon that requires multiple iterations to fix. Problems […]
The relative performance of a single processor has leveled off in the last decade. Built-in instruction-level parallelism is becoming less efficient because issuing more than four instructions in parallel has little effect on most applications. Meanwhile, recent attempts to boost performance have come dangerously close to the energy/power consumption ceiling. Dedicated hardware accelerators may prove […]
How important is it that the history of electronics is passed on from generation to generation of engineers in the ‘right’ way. OK, let’s acknowledge that, as in war, history is always dominated by the victors, not the losers. Let’s also admit that anyone with a career in this business wants its image to be […]