Companies and mask shops already have plans and policies to secure the storage and transmission of sensitive layout VLSI data. These include confidentiality and non-disclosure agreements, and encryption. However, traditional VLSI file formats such as GDSII never popularized the type of constructs that facilitate intellectual property (IP) protection. The OASIS format does have these constructs. […]
Nanometer scaling severely inhibits the path to achieve sustainable yield. In response more responsibility for forecasting potential failures must shift to design for manufacturing (DFM) methodologies that can be applied early in the design process. Yet, while these hold much promise, manufacturing test and failure analysis remains at the forefront of determining why chips fail. […]
Introduction Considerable effort is being exerted to improve the quality and success of system-on-chip (SoC) designs. Given the demand for more and more features, lower power requirements, and need for blazing speeds to handle increasing data for video and other hungry applications, it is no surprise that complex SoCs are becoming harder to verify. A […]
Introduction A synthesized eye diagram begins with an accurate TDT measurement of a linear device. The validity of this approach has been proven across a number of case studies and is now commonly accepted in the communication industry. The measurement allows the device’s eye response to be accurately generated by an advanced synthesis algorithm such […]
We end the year with an issue of EDA Tech Forum that places perhaps more emphasis on design for manufacture than any before it, with opinions from Gartner Dataquest, Mentor Graphics and Applied Materials. These give readers a chance to view this often controversial and misunderstood area from three different but important perspectives: those of […]
Semiconductor devices are being fabricated with features that are less than half the wavelength of the available lithography exposure tools. Increasing circuit density has improved the complexity and performance of ICs but also led to serious patterning proximity effects. These effects make the chips almost impossible to fabricate without optical proximity correction (OPC) technology. Thus, […]
Design teams are becoming increasingly concerned at the growing disparity between the capacity of silicon in the latest processes and the design and verification capabilities of simulation tools. A number of trends are now converging to enable a step function increase in verification to complement and extend the debug and verification capabilities of HDL simulators. […]
The efficient management and synchronization of design data is now a necessity and no longer something that is a ‘nice-to-have’. Design complexity continues to increase with one result being that development spreads across several groups (often in different places). A project may also have several thousands design files generated by various tools from different vendors […]
The network-on-chip (NoC) design paradigm is seen as a way of enabling the integration of an exceedingly high number of computational and storage blocks in a single chip. But its adoption and practical implementation face important and unsolved issues related to design methodologies, test strategies, and dedicated CAD tools. The System-on-a-Chip Research Lab at the […]
If one thing has become clear as process geometries have gone below one micron, it is that the traditional development model is broken. It seems only recently that companies were talking about adopting a greater ‘customer focus’, but even the linear sequence of first, finding out what the client wants; second, getting your designers to […]
