April 26, 2024
Yield Loss

PID yield loss countered by path-based antenna verification

Plasma induced damage (PID) in gate oxide is a threat to MOSFET circuit yield and reliability. How can you effectively combat this issue?
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February 8, 2023
Nebabie Kebebew is a senior product manager at Siemens EDA.

How to migrate SoC design to the cloud

Moving part of all of a design flow to the cloud involves careful preparation and evaluation as there is no 'one-size-fits-all'.
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September 6, 2022
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Let there be no misunderstanding: Verifying CXL cache coherency

How to work with the Compute Express Link and protocols such as MESI to maintain cache coherency.
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March 21, 2022
Tom Anderson is a technical marketing consultant working with multiple EDA vendors, including AMIQ EDA. His previous roles have included vice president of marketing at Breker Verification Systems, vice president of applications engineering at 0-In Design Automation, vice president of engineering at IP pioneer Virtual Chips, group director of product management at Cadence, and director of technical marketing at Synopsys. He holds a Master of Science degree in Computer Science and Electrical Engineering from M.I.T. and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst.

Executable specifications boost SoC and IP efficiency

Automating executable specifications as they evolve can deliver major efficiencies.
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