Lew Counts It is not unusual for analog circuit designers to exhibit a wistful air of ‘been there, done that’, even if you would never catch them wearing the t-shirt. That goes double for Lewis Counts, vice president of analog technology at Analog Devices and a fellow with the sector giant. “There are things they’re […]
Increasing system complexity is forcing design teams to avoid errors during the process of system refinement and reduce ambiguities during system implementation to a minimum. On the other hand, the system design approach they choose must enable a project to advance rapidly through all stages of refinement from an algorithmic model to a real system-on-chip […]
We have entered the era of the multi-processor system-on-chip (MPSoC) but it remains a major frustration that, for a technology that is so imminent and so necessary, there is as yet no real vision out there that goes beyond the parochial. Yes, ‘point’ issues are also being addressed, but we need to define the concept, […]
The paper outlines the criteria upon which an OEM should make its selection of a third-party PCB design supplier. It groups these into three main categories. Staff with appropriate technical and communications skills. Comprehensive and fully documented design processes (ranging from the use of consistent design strategies to approaches to component library maintenance). Tool support […]
Design for manufacturing (DFM) sign-off is a required step in most deep sub-micron technology design environments. However, there is no common methodology for DFM sign-off. We believe DFM should not only give an estimate of the yield, but should also point out where failures are most likely to occur, and where designers can improve their […]
This paper describes a random test generation strategy we are using to complement the verification of upcoming generations of processor. SystemVerilog provided the means to define the functional coverage of our design and to employ the shadow modeling technique, significantly improving our verification flow. Shadow modeling is a reliable method for proving the functionality of […]
Today, most SoC designs include both digital and analog components on the same chip, taking advantage of nanometer geometries. This demands that the current design flow bottleneck due to analog verifi-cation and integration is addressed in ways that enable this process to be completed both thoroughly and efficiently. SPICE simulation was accurate but slow and […]
For a design targeted at the 130nm process node or below, the cost of a dedicated mask-set is getting brutal. At 130nm itself, a semiconductor company is likely to pay between $500,000 and $600,000 per set. That price tag rises to around $1m at 90nm, and to $1.5m at 65nm(Figure 2). One recent forecast for […]
Network-on-chip (NoC) could prove to be an effective methodology that addresses interconnect roadblocks to the development of more complex systems-on-chip. However the term covers many approaches, some of which – simple enhancement to existing bus technologies, the costly adaptation of theoretical networking concepts – fall short either in terms of performance or NREs. The article […]
System-level architectural decisions made before any RTL code has been written have a much larger impact on overall system energy than RTL-level, gate-level, or circuit-level tweaks. The Xenergy tool from Tensilica estimates energy for a processor subsystem (processor, caches, local memories) based on the application code that will run on that subsystem. Designers can thus […]