EDA Topics

March 1, 2008

A question of freedom

Although no EDA company counts among its membership (for good practical reasons), it is fair to describe the US Consumer Electronics Association (CEA) as one of technology’s most broadly representative trade bodies. From retailers and brand holders to the hardware and software companies that directly supply components for CE products, the CEA has a position […]

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March 1, 2008

Active power management for configurable processors

ARC International is one of the largest suppliers of configurable processor technology. It licenses patented configurable multimedia subsystems and CPU/DSP processors that are used to design differentiated products. They are optimized for use in systemson- chip (SoCs) that consume less power, are less expensive to produce and require protection from cloning. The ARC Energy PRO […]

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March 1, 2008

Efficient packet header parsing using an embedded configurable packet engine

Cswitch’s CS90 Configurable Switch Array device has an interconnect structure, the dataCrossconnect network, that delivers bandwidth at 40- 100Gbps for packet-based applications. For packet handling tasks, the chip includes embedded configurable blocks, Configurable Packet Engines, that support functions such as frame parsing, CRC and hashing, and fast address look-ups, all at up to 1GHz. For […]

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March 1, 2008

ESL at the inflection point

Electronic system level (ESL) design is moving to a new stage in its development, advancing from a proof-of-concept environment to one that is seeing its adoption and deployment at the forefront of design. The article terms this shift ‘ESL 2.0’. The reason for this goes beyond mere marketing hype. Inherent in the transition defined above […]

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March 1, 2008

High quality scan test with minimal pins

Changes in defect distribution, increasing design complexity and pressures from the specialist I/O and packaging arenas are creating a dilemma during component test. On the one hand, the generation of more test patterns would appear to be necessary; but on the other, fewer test ports are available. The article describes a strategy for addressing this […]

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December 1, 2007

Mastering the memory maze

Since the early 1980s,most of the semiconductor business has been enthralled by the microprocessor, the PC and commodity DRAMs. For all the talk of potential ‘better markets’ and ‘more profitable businesses to be in’, PCs and their brethren came to represent 35- 40% of the industry’s output. They constituted the prime platform for not only […]

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December 1, 2007

Portable multimedia SoC design: a global challenge

Today more than ever, the difference between design success and failure resides in engineers’ ability to master all critical design factors at once. Meanwhile, systems-on-chip (SoCs) represent a multidisciplinary challenge that spans the entire flow from architecture through design to test and finally mass production. For portable applications in particular, SoCs present especially stringent constraints […]

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December 1, 2007

The simulation and design of software-defined radios

The paper discusses the simulation, design, and test of software-defined radios (SDRs), initially using a legacy 16QAM waveform, followed by a new SDR waveform -orthogonal frequency division multiple access (OFDMA). The SDR system’s error vector magnitude (EVM) is first analyzed and its performance is compared with the legacy waveform results. The implementation also includes the […]

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December 1, 2007

UPF delivers on power

Long before the first portable computer batteries exploded, and even before anyone had the first visions of building massive data centers in the cold northwestern states of Oregon,Washington and Alaska, power consumption by electronic devices was a tough problem for chip designers. The difference now is that we are trying to manage power in ever-smaller […]

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December 1, 2007

Using a ‘divide and conquer’ approach to system verification

Today’s increasingly complex designs typically need to undergo verification at three different levels: block, interconnect and system. There are now well-established strategies for addressing the first two, but the system level, while in many ways the ultimate test, remains the weakest link in the verification process. System verification normally begins only after a prototype board […]

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