The paper discusses the simulation, design, and test of software-defined radios (SDRs), initially using a legacy 16QAM waveform, followed by a new SDR waveform -orthogonal frequency division multiple access (OFDMA). The SDR system’s error vector magnitude (EVM) is first analyzed and its performance is compared with the legacy waveform results. The implementation also includes the […]
Today’s increasingly complex designs typically need to undergo verification at three different levels: block, interconnect and system. There are now well-established strategies for addressing the first two, but the system level, while in many ways the ultimate test, remains the weakest link in the verification process. System verification normally begins only after a prototype board […]
Since the early 1980s,most of the semiconductor business has been enthralled by the microprocessor, the PC and commodity DRAMs. For all the talk of potential ‘better markets’ and ‘more profitable businesses to be in’, PCs and their brethren came to represent 35- 40% of the industry’s output. They constituted the prime platform for not only […]
While DDR3 SDRAM offers speed and low-power benefits, the fly-by termination topology defined by the JEDEC specification for DDR3 SDRAM DIMMs creates interesting challenges for FPGAs. The JEDEC topology significantly reduces the simultaneous switching noise that plagues high-frequency parallel interfaces, but also introduces the need for read and write leveling to compensate for the deliberate […]
The correlation of a statistical analysis tool to hardware depends on the accuracy of underlying variation models. The models should represent actual process behavior as measured in silicon. This paper presents an overview of test structures for characterizing statistical variation of process parameters. It discusses the test structure design and characterization strategy for calibrating random […]
Simultaneous Switching Noise (SSN) is the voltage fluctuation caused by the simultaneous switching of groups of output chip I/O drivers that drive high slew rate signals. It has an impact on I/O and core power supply lines and on signal lines, and is an increasingly important challenge for designs that incorporate high performance interfaces, such […]
Verification has become one of the main bottlenecks in hardware and system design. Several verification languages, methods and tools addressing different issues in the process have been developed by EDA vendors in recent years. This paper takes the industrial user’s point of view to explore the difficulties posed when introducing new verification methods into ‘naturally […]
Introduction Burgeoning design complexity has greatly increased the scale of the verification effort. At the same time, there is a widening gap between the growth in vital activities such as functional verification and the ability of tools and methodologies to fulfill such tasks efficiently. If we fail to close that gap, the potential impact on […]
Concurrent multi-corner, multi-mode analysis and optimization is becoming increasingly necessary for sub-65nm designs. Traditional P&R tools force the designers to pick one or two mode corner scenarios due to inherent architectural limitations. As an example of the problem, a cellphone chip typically needs to be designed for 20 mode/corners scenarios. In the absence of a […]
There must be a better way to keep track of electronic engineering software licenses. EDA tools are very expensive, essential to R&D work, and must be properly maintained to ensure that commercial designs are completed on-schedule. Nevertheless, companies traditionally set aside little management time to put formal control systems in place for these assets. Consider […]