Electronic system level design for embedded systems
There is a growing productivity gap in the design of embedded systems. One recent survey estimated that the number of lines of embedded code written per year is growing at a rate of 46% a year, although the number of developers available to write it is growing at only 7.5%.
The problem is further compounded by the facts that embedded systems are now ubiquitous in their use across a number of markets with stringent cost, time-to-market and reliability requirements, and that traditional hardware-centric methodologies introduce inefficiencies and high risks of failure to the design flow by requiring multiple iterations.
A major issue here is the use of multiple models for the processor used at the heart of embedded system design. The article highlights an alternative methodology already gaining traction in key markets based on software virtual prototyping and an appropriate, individual, cycle-accurate, high performance processor model that can deliver greater reliability and speed project flows by enabling hardware/software co-design.
Design abstraction to the electronic system level has been ‘just around the corner’ for a decade.Why is it taking so long? In fact, many observers believe that one of the keys to making ESL real for mainstream engineers is for it to better solve the critical needs of embedded systems design.
Embedded systems are notoriously difficult to design and verify. They have particularly stringent intellectual property (IP) needs: high quality, plus fast performance, plus extreme accuracy. The embedded designer needs methodologies and IP that are supported by advanced tools to achieve the higher level of productivity that comes from automating development and verification at the system level. During the last few years, it is true that vendors of embedded systems design tools have made substantial progress in meeting designers’ needs, but even as vendors have done so, the overall problem has grown larger and more complex. In particular, we now live in a world where embedded systems are truly ubiquitous. They control everything from the air-conditioning in your home to the reception on your large widescreen TV to the airbags and safety warning systems in your car. The inevitable consequence of this is that their cost effective, high quality design has become one of the great challenges of the decade. Let’s look at some of the numbers.
A 2005 report by the BCC Research Group, The Future of Embedded Systems Technology, judged that the global market in embedded systems had an annual growth rate of 14% and projected that it would reach a value of $88B by 2009 (Figure 1). Venture Development Corporation (VDC) principal Chris Lanfear recently estimated the tools market for embedded design to be roughly $1.9B, and said that the subset of this covering mobile applications has a 35% compound annual growth rate.
Figure 1. Global embedded systems market, 2003-09
Lanfear further noted a stark contrast inherent in the rapid growth in the software content of embedded designs. He said that the amount of code written per project has risen 46% annually in the 1980-2005 period, but the number of developers hired to write that code has risen only 7.5% annually during that time. The VDC survey cites this as one of the primary reasons why more than a third of all embedded projects are late while nearly 13% are canceled. If embedded hardware designers need high quality IP and good tools badly, embedded software developers need them desperately. Many of the design challenges of embedded systems stem from the silicon encapsulation of processors, software, and subsystems within a single integrated circuit. Through this integration, semiconductor products are redefined to include the chip plus the software. At last year’s Future Horizons Electronics Forum, AMD fellow Robert Ober said, “At the 45nm node and beyond, silicon providers not only have to deliver software and the host hardware, but they have to develop it at higher levels of abstraction to create stable configurable platforms.”
In this context, any viable ESL solution needs to address the following problems. It must:
- Support rapid ‘what if ’ architecture analysis and performance- driven architecture optimization;
- Have the speed and cycle accuracy to support all types of pre-silicon software development;
- Provide standards fluency, to facilitate interoperability within the major steps of the design flow – architecture design, software development, implementation, and system verification – as well as distribution to customers.
Traditional, sequential ‘hardware-then-software’ design methodologies and the tools that support them are not equal to the task. The traditional process begins with obese Word documents describing the requirements and the architecture, perhaps augmented by a few models. The architecture is ‘optimized’ through laborious trial and error. Next, the systems architect has to reinterpret and disambiguate all this information to implement the hardware portions of the design. Then, everything is reinterpreted and disambiguated again for the software development phase with point tools providing the automation at each step. This sequence of reworks has the undesirable side effects that there is an increasing risk that errors will be introduced at each step, and that definitive testing of system performance and throughput will be delayed until the software portion of the design is complete.
The traditional pantheon of point tools largely for the register transfer level (RTL) of abstraction is not much help in a world of software-heavy embedded systems. Point tools were created and optimized to facilitate detailed hardware design, and, inevitably, attempts to create ESL design tools based on them inherit a hardware- centric view of the world. For example, if the hardware is specified using an application programming language like C or C++, and then constrained to an RTL-compatible subset, what has been substantially gained over using Verilog or VHDL?
Embedded systems design requires a new paradigm of ESL solutions. Its tools and models must deliver the speed and accuracy required to perform quantitative architectural exploration and optimization. They must ultimately provide a hardware prototype equivalent in software, so that embedded software development can begin in parallel with hardware development.
Unfortunately, early attempts to provide solutions for embedded systems design addressed the challenge by providing multiple models, or ‘views’, of the processor, the heart of the embedded system. Designers had to wrestle with the ‘programmer’s view’, the ‘programmer’s view with timing’, the ‘cycle-accurate view’ and so on. Each of these views traded off performance for accuracy in an attempt to cover all needs. This multiple model approach is simply untenable in a real design flow, as multiple models are functionally out-of-sync by definition, and present conflicting views of end-system functionality and performance.
At the September 2005 Embedded Systems Conference in Boston, Robert Oshana, a Texas Instruments engineering manager, taught a class on real-time embedded systems where he clearly demonstrated the cost of operating without cycle accuracy over actual silicon for an embedded system design project. He said that more than 16 weeks on a TI project with a total duration of 42 weeks had been spent re-optimizing code and algorithms as a result of performance surprises stemming from inconsistent views of accuracy at various points in the design flow. One high performance and cycle-accurate model would have literally saved TI months. Virtual system prototyping with ‘one source’ processor models Enabling true concurrent hardware/software design is a critical requirement for the growth of the embedded systems sector. Consumer products need to achieve this goal so that the toughest cost control and time-to-market requirements can be fulfilled; safety and mission-critical applications must achieve it to meet the enormous demands in those markets for quality and reliability. One methodology that delivers such a co-design capability and which is having marked success for embedded systems in wireless, consumer and automotive markets is virtual system prototyping (VSP) with ‘one source’ virtual processor models.
Figure 2. VSP in practice
A VSP is a software-simulation-based, timing-accurate, ESL model of the embedded system. Developed and used first at the architectural level, it then serves as an executable ‘golden’ reference model throughout the design cycle. Figure 2 (p16) shows this process in action and Figure 3 (p16) illustrates how it integrates into and improves the design flow.
A VSP typically contains multiple cycle-accurate virtual processor models that run the same compiled and linked target code as the real hardware, providing accurate predictions of the system’s realworld behavior. Cycle-accurate models for buses, peripherals and other portions of the hardware design are added so that the VSP models the complete behavior of a multi-core embedded system. VSPs enable architectural exploration by allowing hardware and software components to be mixed and matched. Accurate measurements that model real-world behavior allow system architects to make accurate hardware/software tradeoffs early in the development process.When the initial system architectural model is built, it becomes the executable system specification that drives the concurrent development of the detailed hardware and software implementations.
One of the keys to effective virtual system prototyping is the concept of one, golden model, or a ‘one source’ processor model, that lies at the heart of the embedded system. This approach requires that the virtual processor models be both very high speed and cycle-accurate. Although some solutions providers minimize the importance of timing accuracy, the reality is that embedded systems have performance-critical timing interactions within the processor and between the processor and peripherals. If ignored, these can result in significant software rework and an increased risk of design respins.
There are many levels of software in modern embedded systems. At the lowest level are device drivers that perform timing-critical interactions with system hardware. Above the device drivers lie operating systems, middleware, and application-level software. All levels of software development move forward best when they can use the same high-speed, cycle-accurate processor model.
Figure 3. VSP within the design flow
Solutions that require the software developer to juggle multiple processor models (typically high-speed models with crude or no timing for the application development, and slow, cycle-accurate models for device driver development) introduce inefficiencies and increase the probability of serious error. All too often, the multiple-model approach results in significant re-work when porting the software to the real hardware.
To really help software developers, virtual system prototyping solutions need to be based on the concept of no compromise between high performance and high accuracy models. VaST Systems’s single core VSP-based simulation can achieve anywhere between 50-200MIPS, while multi-core systems with tiered memory structures and multi-level buses can be simulated at 10-100MIPS, depending on the configuration. All this is undertaken with cycle accuracy, and running on a standard PC.
The ability of the VSP to run real software workloads yields invaluable information in guiding the system architects to an optimal architecture, including:
- Bus contention and bandwidth utilization;
- Processor capabilities and utilization;
- Working set match/mismatch to cache size and set associativity;
- Latency in system response to internal and external events;
- Correlation of external, hardware, and software conditions and events;
- Transaction and algorithm throughput.
There is no end in sight to the position of embedded systems design as one of the fastest growing areas in electronic design, nor to the pressures upon it to meet ever-tighter design cycles and everincreasing complexity. In this context, traditional sequential methodologies that use multiple models of the same processor and the tools that support this type of flow are already failing to meet the needs of today’s designs, and this situation can only be expected to worsen if it is not addressed.
The concept of virtual system prototyping with one source for high performance, cycle accurate processor models is one methodology that is being used with increasing success to meet this challenge.
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