December 1, 2008

No silicon leapfrog

Andre Geim When you were young, did you enjoy bouncing around on a trampoline? If so, try this for size. Imagine a membrane about 275 miles long, one mile deep and an average of 10 miles wide. These dimensions matter. Because this sheet of material covers the entire Grand Canyon—and before you go bouncing on […]

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June 1, 2008

STIX to the task

Before 2001’s historic downturn, the semiconductor industry was primarily driven by the corporate and enterprise markets. This bias led to a somewhat predictable three-year business cycle of peaks and troughs. Corporate buying practices, technology requirements and IT replacement policies are all relatively easy to predict—right down to the nature of the semiconductors that underpin the […]

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June 1, 2008

Migration of the Cell Broadband Engine to 45nm SOI

The paper describes some of the main challenges in the latest process shrink for the Cell Broadband Engine, developed jointly by IBM, Sony and Toshiba. The authors show how the move from a 65nm to a 45nm SOI process was achieved by concentrating on four primary goals: automating the migration; setting a 30% power reduction […]

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June 1, 2008

Multi-corner multi-mode signal integrity optimization

Signal integrity (SI) is an ever-growing problem as more interconnect effects and fast clocks increase the chances of crosstalk noise and glitches as well as unexpected signal delays. There has been a significant increase in SI-related timing violations due to the increasing influence of lateral wire capacitance in designs at 65 and 45nm. A fast-increasing […]

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March 1, 2008

The veteran competitor

In his early days in the semiconductor industry, Morris Chang Morris Chang was one of the “non-Texans” to Texas Instruments and was a manager struggling with the question of how to get individual transistor yields to somewhere around three or even four per cent. One of his colleagues – another immigrant to the Lone Star […]

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March 1, 2008

Towards an infrastructure for profitable DFM

The real objective of design for manufacturability (DFM) is to improve a product’s profitability and manufacturing predictability for its market window and unit volume by optimizing tradeoffs between design costs and manufacturing improvements according to a holistic, lifetime view of the product. Current DFM practice often falls far short of that goal. For instance, the […]

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December 1, 2007

Portable multimedia SoC design: a global challenge

Today more than ever, the difference between design success and failure resides in engineers’ ability to master all critical design factors at once. Meanwhile, systems-on-chip (SoCs) represent a multidisciplinary challenge that spans the entire flow from architecture through design to test and finally mass production. For portable applications in particular, SoCs present especially stringent constraints […]

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September 1, 2007

Characterizing process variation in nanometer CMOS

The correlation of a statistical analysis tool to hardware depends on the accuracy of underlying variation models. The models should represent actual process behavior as measured in silicon. This paper presents an overview of test structures for characterizing statistical variation of process parameters. It discusses the test structure design and characterization strategy for calibrating random […]

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June 1, 2007

Implementation of a DFM checker for 65nm and beyond

Design for manufacturing (DFM) sign-off is a required step in most deep sub-micron technology design environments. However, there is no common methodology for DFM sign-off. We believe DFM should not only give an estimate of the yield, but should also point out where failures are most likely to occur, and where designers can improve their […]

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March 1, 2007

Confronting chip assembly challenges

Until recently, hierarchical design flows have been favored for the implementation of multi-million gate SOCs. However the rapid increases in design size brought on by nanometer process geometries have seen engineers seek to cope with the inherently block-based nature of such flows by seeking greater concurrency between the block implementation and chip assembly stages in […]


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