The demands of manufacturing closure at advanced process nodes make the traditional design-then-fix flow unmanageable. At 28nm and below, designers need a solution that can address manufacturing issues at any point in the design process, enabling a true correct-by-construction methodology. An effective solution must provide design-rule-check and design-for-manufacturing analysis using the actual foundry-approved signoff rules [...]
Product engineering services can be efficiently outsourced and even the biggest players are doing it, says Michel Villemain
This year's Design Automation and Test in Europe conference heard from a broad range of users and suppliers about the challenges to and solutions for getting optimal yields at advanced process nodes, particularly as the industry advances toward 22nm. This article recaps presentations by four executives at the Dresden-hosted event: Pierre Garnier of Texas Instruments, [...]
The time-dependent dielectric breakdown (TDDB) of inter-metal dielectrics on large-scale chips is becoming an increasingly important reliability issue across several semiconductor markets. This mechanism can cause early failures in use and is difficult to detect by traditional test, and hard to control by traditional reliability techniques.
Designers have been using dummy fill to address design for manufacturing for some time, but the process of simply wallpapering shapes into a design's "white space" to help it maintain planarity can no longer cope with the complex challenges presented at today's advanced process nodes. Not only is planarity harder to maintain, but there are [...]
The article offers a case study of the DFM planning and methodology applied during a shrink of Cambridge Silicon Radio's UF6000 system-on-chip from the 130nm to 65nm.
DFM is essential to differentiating your products in the market, says Luigi Capodieci
Engineering managers need to get their priorities in order for incoming process nodes, says analyst Gary Smith
The purpose of this special issue of EDA Tech Forum is to try and cut through some of the confusion and even frustration that surrounds DFM as a concept. We cannot promise “DFM for Dummies,” but we do hope to give you a sense of how you might manage the process.
A greater proportion of the layout requires more precise extraction at the 32nm and 28nm process nodes, so rules-based extraction tools can no longer deliver the accuracy needed to confirm acceptable electrical performance. Given the nature of parasitic elements in analog and mixed-signal (AMS) system-on-chip designs, designers need a parasitic extraction tool that provides gate-level, [...]
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