verification IP

Cache coherency implemented in hardware increases the verification effort. VIP-based strategies are described with particular reference to ARM protocols.

Trying to balance your use of simulation and FPGA prototyping is tough. Acceleration used with Accelerated VIP offers simulation-like visibility and debug with near FPGA performance.

How should you quiz your verification IP vendor to get the right VIP for your needs? Synopsys' Neill Mullinger details a checklist of the key points to raise.

Mentor’s Dennis Brophy, Cadence’s Stan Krolikoski and Synopsys’ Yatin Trivedi describe how you can prepare to adopt Accellera’s Universal Verification Methodology.