Volumes

December 1, 2009

Silicon test moves up the food chain

Technological advances are often driven by the need to simplify and control a task. Silicon test is a good example. Its requirements are continuously increasing in complexity and this process drives the development and adoption of automated test strategies. A thorough approach to manufacturing test is essential to the delivery of high-quality devices. A whole-chip […]

December 1, 2009

Raising the bar to manage R&D and ROI

Semiconductor companies are hustling to grow revenues, stay on the razor’s edge of technology and remain one step ahead of their customers’ needs. All this is going on while the industry is undergoing wrenching change. The end of 2009 finds the chip business at a crossroads. It has been more than 60 years since the […]

September 2, 2009

Part 3 – A unified, scalable SystemVerilog approach to chip and subsystem verification

The article describes LSI’s work on the use of a single SystemVerilog-based (SV) verification environment for both the chip and its submodules. The environment is based on SV’s Advanced Verification Methodology (AVM) libraries, although alternatives are available. One particular reason for choosing AVM was that LSI wanted to leverage its transaction-level modeling capabilities as well […]

Article  |  Tags: , , ,
September 1, 2009

Stepping up

During the CEO Panel at this year’s Design Automation Conference, the men leading the three largest EDA vendors stressed that their industry can do well in a slump because it both contributes to the ongoing battle against technological limits, and enables the delivery of ever greater efficiency. But another, parallel question raised by this year’s […]

Article  |  Tags: , , ,
September 1, 2009

Reading the runes

When we first reviewed the consumer electronics market at the beginning of the year, there were still hopes that growth could remain statistically flat despite global economic woes. However, at the beginning of the summer, the Consumer Electronics Association revised its forecast down from January’s -0.7% to -7.7%, implying total factory-gate sales of $165B. The […]

Article  |  Tags: ,
September 1, 2009

Pushing USB 2.0 to the limit

USB offers many advantages for use on embedded systems, although software developers remain concerned about the additional complexity it can bring to an application. For example, software drivers for SPI, RS-232 and other traditional serial protocols typically involve little more than read and write routines, while USB software drivers can span thousands of lines, incorporating […]

Article  |  Tags:
September 1, 2009

Implementing a unified computing architecture

Netronome offers a range of programmable Network Flow Processors, which deliver high-performance packet processing and are aimed at designers of communications equipment whose requirements extend beyond simple forwarding. Many network processors and multicore CPUs lack L4-L7 programmability or cannot scale to 10Gbit/s and beyond. Netronome’s flow processors are powered by 40 programmable networking cores that […]

September 1, 2009

Extending UPF for incremental growth

Erich Marschner Accellera’s Unified Power Format (UPF) is in production use today, delivering the low-power system-on-chip (SoC) designs that are so much in demand. Building upon that success, IEEE Std 1801-2009 [UPF] offers additional features that address the challenges of low-power design and verification. These include more abstract specifications for power supplies, power states, and […]

Article  |  Tags: , ,
September 1, 2009

Linux Nucleus… Or both

Until recently, operating system (OS) specification for embedded systems has been seen largely as an ‘either/or’ exercise. Similarly, OSs that have their foundations in the embedded market and those that have grown out of desktop computers have been seen as competing rather than complementary technologies. Cost and performance criteria within specifications will often lead to […]

Article  |  Tags: , , ,
September 1, 2009

Ensuring reliability through design separation

System designs have traditionally achieved reliability through redundancy, even though this inevitably increases component count, logic size, system power and cost. The article describes the design separation feature in Altera software that seeks to address these as well as today’s conflicting needs for low power, small size and high functionality while maintaining high reliability and […]

Article  |  Tags: ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors