The architectures that underpin today’s traditional place-and-route tools are showing their age, largely because their static timing analysis engines cannot handle more than two mode/corner scenarios. Thus limited, the software struggles to effectively implement low-power design techniques beyond such established concepts as clock gating and multiple threshold voltages. Designers run into difficulties when trying to […]
Chemical mechanical polishing (CMP) has traditionally been considered an enabling technology. It was first used in the early 1990s for BEOL metallization to replanarize the wafer substrate thus enabling advanced lithography, which was becoming ever more sensitive to wafer surface topography. Subsequent uses of CMP included density scaling via shallow trench isolation and interconnect formation […]
Andre Geim When you were young, did you enjoy bouncing around on a trampoline? If so, try this for size. Imagine a membrane about 275 miles long, one mile deep and an average of 10 miles wide. These dimensions matter. Because this sheet of material covers the entire Grand Canyon—and before you go bouncing on […]
The Oasis file format is intended as the long-term successor to GDSII, which is now 30 years old. However, even though the first specification for Oasis was released in 2004, there is still a great deal of confusion and ignorance surrounding the standard. The article looks at the background of Oasis’ development, identifies its strengths […]
Signal integrity (SI) is an ever-growing problem as more interconnect effects and fast clocks increase the chances of crosstalk noise and glitches as well as unexpected signal delays. There has been a significant increase in SI-related timing violations due to the increasing influence of lateral wire capacitance in designs at 65 and 45nm. A fast-increasing […]
Before 2001’s historic downturn, the semiconductor industry was primarily driven by the corporate and enterprise markets. This bias led to a somewhat predictable three-year business cycle of peaks and troughs. Corporate buying practices, technology requirements and IT replacement policies are all relatively easy to predict—right down to the nature of the semiconductors that underpin the […]
The paper describes some of the main challenges in the latest process shrink for the Cell Broadband Engine, developed jointly by IBM, Sony and Toshiba. The authors show how the move from a 65nm to a 45nm SOI process was achieved by concentrating on four primary goals: automating the migration; setting a 30% power reduction […]
In his early days in the semiconductor industry, Morris Chang Morris Chang was one of the “non-Texans” to Texas Instruments and was a manager struggling with the question of how to get individual transistor yields to somewhere around three or even four per cent. One of his colleagues – another immigrant to the Lone Star […]
The real objective of design for manufacturability (DFM) is to improve a product’s profitability and manufacturing predictability for its market window and unit volume by optimizing tradeoffs between design costs and manufacturing improvements according to a holistic, lifetime view of the product. Current DFM practice often falls far short of that goal. For instance, the […]
Today more than ever, the difference between design success and failure resides in engineers’ ability to master all critical design factors at once. Meanwhile, systems-on-chip (SoCs) represent a multidisciplinary challenge that spans the entire flow from architecture through design to test and finally mass production. For portable applications in particular, SoCs present especially stringent constraints […]
