signal integrity

April 5, 2012

Overcoming increasing PCB complexity with automation

Advanced PCB and IC technologies have to be matched with advanced design and analysis tools if companies are going to produce board designs that are right first time, on time.
May 25, 2011

Fundamentals of Signal Integrity Analysis

New to Signal Integrity analysis, or just need to brush up on the fundamentals? If so, this white paper is aimed at you. This white paper starts at the very basic, actually before the fundamentals, answering the question “What do I need to know?” The paper begins by identifying and analyzing critical nets. Next, it […]

Whitepaper  |  Topics: PCB - Design Integrity  |  Tags: , ,
May 21, 2011

Plane Noise Effects

High-speed digital drivers need a good source of power to produce clean, fast signals. For a driver to switch the state of a signal in tens or hundreds of picoseconds, the power plane must be able to supply significant current over a wide bandwidth. The surge in current creates voltage fluctuations in the power distribution […]

September 10, 2010

Designing a PCB for power integrity

Signal integrity (SI) issues have been around for a while, the result of ever-faster edge rates. Both SI and PI problems manifest themselves as data errors. Indeed, PI problems are often misdiagnosed as SI problems. As such, an understanding of power delivery issues is essential to the success of any board project, as is a [...]
Article  |  Topics: PCB - Design Integrity  |  Tags: ,
June 1, 2009

Reducing system noise with hardware techniques

Circuit noise problems can originate from a variety of sources. By carefully examining attributes of the offending noise you can identify it’s source, thereby making noise reduction solutions become more apparent. There are three subcategories of noise problems: device, conducted and radiated noise. If an active or passive device is the major noise contributor, you […]

November 1, 2008

Board-level timing analysis

This paper builds on “Timing Numbers In ICX – What do we do with them?” [1]—a paper presented at the 2006 Mentor Graphics User2User conference (and now available for download at the journal’s Web site, www.edatechforum.com). The original paper focused on the need for timing analysis and the theory behind it; this paper takes a […]

June 1, 2008

Multi-corner multi-mode signal integrity optimization

Signal integrity (SI) is an ever-growing problem as more interconnect effects and fast clocks increase the chances of crosstalk noise and glitches as well as unexpected signal delays. There has been a significant increase in SI-related timing violations due to the increasing influence of lateral wire capacitance in designs at 65 and 45nm. A fast-increasing […]

Article  |  Topics: EDA - DFM  |  Tags: , ,

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