PCI Express

February 27, 2018
PCI_Express_logo

Tackling the design challenges of PCIe 5.0

Moving up to PCIe 5.0 speeds demands rethinking everything from silicon design through choice of PCB material and connectors up to track layout and validation.
July 18, 2017
Richard Solomon, technical marketing manager, Synopsys

Using CCIX to implement cache coherent heterogeneous multiprocessor systems

CCIX is a cache coherency protocol, based on PCI Express, for interconnecting high-performance heterogenous multiprocessing systems.
Expert Insight  |  Topics: Embedded - Architecture & Design, IP - Assembly & Integration, Selection  |  Tags: , , ,   |  Organizations: ,
November 2, 2015
Verification IP for greater productivity

How to cut verification time with VIP

This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics' Questa platform.
Article  |  Topics: EDA - Verification  |  Tags: , , , ,   |  Organizations: ,
September 18, 2015
Featured image: PHY VIP Sep 15

How PHY verification kits overcome traditional VIP limitations

Established physical layer verification IP packages focus so much on protocols they miss problems that arise from the broader context. A PHY verification kit bridges the gap.
Article  |  Topics: IP - Assembly & Integration, EDA - Verification  |  Tags: , , , , , , ,   |  Organizations:
June 27, 2014
M-PCIe_fig1

How to use PCI Express in low-power mobile SoCs by exploiting M-PCIe

How to use PCIe in low-power SoCs by swapping the standard PCIe PHY for M-PCIe, defined by MIPI for mobile use
Article  |  Topics: EDA - IC Implementation, IP - Selection  |  Tags: , , , ,   |  Organizations:

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